Semiconductor memory device capable of driving non-selected word lines to first and second potentials

ABSTRACT

A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device having thefunction of executing a reset operation of a word line connected to aspecific memory cell, by driving the word line, in order to return thespecific memory cell, in a memory cell array of a semiconductor memory,from an activated state to a standby state.

Demands for lower power consumption have been increasing in recent yearsin semiconductor devices comprising a semiconductor memory such as adynamic random access memory (hereinafter abbreviated to “DRAM”) inconsideration of battery driving. Therefore, power that is consumed in acircuit for executing the reset operation described above must bereduced as much as possible, too.

The present invention also relates to a semiconductor device for storingdata by storing charges in memory cells and more specifically, to asemiconductor device which sets a word line potential at the time ofnon-selection to a negative potential so as to insure a safe andreliable operation even when a power source voltage is lowered so as tocope with higher circuit integration and even when a transistorthreshold voltage value becomes low.

The present invention also relates to a semiconductor device including aplurality of power source circuits for generating different potentialsby driving a capacitor by an oscillation signal, such as a step-upcircuit (i.e., booster circuit) and a step-down circuit and morespecifically, to a semiconductor device comprising a DRAM having suchpower source circuits.

2. Description of the Related Art

Generally, each of a plurality of memory cells that constitute a memorycell array in the DRAM includes one cell transistor for reading orwriting data and one cell capacitor connected to the source of this celltransistor. The cell capacitor stores a charge depending on the logic“1” or “0” of the data written into the memory cell. A word line isconnected to the gate of each cell transistor so as to supply a voltagenecessary for bringing this cell transistor into an operating state(activated state).

When an N-channel transistor is used as the cell transistor inside eachmemory cell, a threshold voltage between the gate and the source of thisN-channel transistor must be taken into consideration. In other words,when data is written or read by selecting a specific memory cell among aplurality of memory cells, a step-up voltage which is elevated by atleast the threshold voltage between the gate and the source of theN-channel transistor is supplied from a word line to the gate of theN-channel transistor in order to reliably bring the cell transistor inthis specific memory cell from the standby state to the activated state.Furthermore, in order to accomplish a high-speed operation of the DRAM,the cell transistor in the selected memory cell must be quickly returnedfrom the activated state to the standby state after the data is writteninto, or read out, from the selected memory cell.

The operation that supplies a reset signal of a predetermined level fromthe word line to the cell transistor so as to return the cell transistorunder the activated state to the standby state is generally referred toas the “reset operation” of the word line. A technology which sets thelevel of the reset signal (reset level, that is, reset potential)outputted from a word line driver circuit, to a potential of a negativevoltage level (negative potential), but not to the ground potential, hasbeen employed for this reset operation so as to minimize the leakage ofthe charges that are stored in the cell capacitor.

On the other hand, the integration density has become higher and higherin semiconductor memories (semiconductor memory devices) andscaling-down of the memory cell size has been made with a higherintegration density. When the memory cell is scaled-down, a drivingvoltage must be lowered because the withstand voltage of the memory cellbecomes low, and it becomes more difficult to insure a safe and reliableoperation of the memory. Particularly in the case of the memories ofsuch a type in which a capacitor is provided to each memory cell and thecharge storing state and the charge non-storing state in the capacitorare allowed to correspond to the data values, as typified by the DRAM,the charges that are stored in the capacitor gradually drop due to theleakage current of the memory cell, and a re-write operation referred toas “refresh” must be carried periodically. When the memory cell isscaled down, the withstand voltage of the capacitor becomes low, so thata high voltage cannot be applied to the memory cell. In other words, thevoltage of the power source must be lowered. The threshold voltage ofthe transistor must be also lowered with the decrease of the powersource voltage, thereby inviting the problem that the leakage currentwhen the cell transistor is not selected (sub-threshold leak) increasesand the data retaining time becomes short. When the data retaining timebecomes short, the cycle of the refresh operation must be shortened soas to cope with this short time, thereby inviting also the drop ofperformance of the DRAM such as the increase of the refresh current.

On the other hand, attempts have been made in recent years to reduceoperating voltages of the semiconductor devices to improve the operationspeed, to save power and to reduce noise. For instance, a drivingvoltage of 5 V has long been used for the semiconductor devices butrecently, a 3.3 V voltage has been used and this voltage may becomelower in the future. Nonetheless, such a voltage alone is not sufficientto insure stability of the operation, and a higher voltage and anegative voltage become necessary. Therefore, a step-up power sourcecircuit (i.e., boosting power source circuit) and a step-down powersource circuit are provided inside the semiconductor device so as togenerate the necessary voltages in the semiconductor device. The DRAM,in particular, has been developed by simplifying as much as possible theconstruction so as to attain a high integration density but recently, ahigh operation speed has become also an important object in addition tothe high integration density.

In order to make the problem that is encountered when the resetpotential of the word line is set to the negative potential during thereset operation of the memory cell in the DRAM, more easily understood,the construction and operations of DRAMs, etc., according to the priorart that have the function of executing the reset operation will beexplained with reference to FIGS. 1 to 5 of the accompanying drawings inthe later-appearing “BRIEF DESCRIPTION OF THE DRAWINGS”.

FIG. 1 is a circuit diagram showing the construction of the firstexample of a semiconductor device having the function of setting a resetpotential to a negative potential according to the prior art, and FIG. 2is a timing chart useful for explaining the operation of the prior artdevice shown in FIG. 1. In this case, the drawings show the circuitconstruction for driving the word lines in the semiconductor device tosimplify the explanation.

A word line driver 280 is shown disposed in FIG. 1 for supplying adriving signal SWL of a predetermined voltage level to the word lineconnected to the gate of the cell transistor inside the memory cell.This word line driver 280 includes an inverter comprising a P-channeltransistor 285 and an N-channel transistor 290 for outputting thedriving signal SWL on the basis of a selection signal, and an N-channeltransistor 295 for clamping the word line at a predetermined reset level(reset potential) on the basis of a reset control signal SWDX. Thesource of each N-channel transistor 290, 295 is connected to a powersource (negative power source) having a negative voltage Vnwl forresetting the word line. The N-channel transistor 295 becomes operative(ON) during the reset operation of the word line, and the output levelof the driving signal SWL outputted from the word line driver circuit issubstantially equal to the potential of the negative power source.

In FIG. 1, there is further disposed a word line driver control circuit180 for controlling the voltage level of the driving signal SWL bysupplying a high voltage side power source signal SWDZ to the P-channeltransistor 285 of the word line driver 280. This word line drivercontrol circuit 180 includes an inverter comprising a P-channeltransistor 170 and an N-channel transistor 175. The source of theP-channel transistor 170 is connected to a power source of a step-upvoltage Vpp, and the source of the N-channel transistor 175 is connectedto the negative power source having a negative voltage Vnwl. Here, thehigh voltage side power source signal SWDZ of the step-up voltage Vpp orthe negative voltage Vnwl is supplied to the high voltage side powersource of the word line driver 280 on the basis of the control signalinputted from a node n01 on the input side of the inverter.

The operation of the semiconductor device of FIG. 1 is shown in thetiming chart of FIG. 2. As is obvious from FIG. 2, when the memory cellis in a standby state, the signal level at the node n01 and the signallevel at each portion, are as follows.

The signal level at the node n01=Vpp (high voltage level (“H (High)”level), the high voltage side power source signal SWDZ=Vnwl (low voltagelevel (“L (Low)” level), the selection signal MWL=Vpp, the resetcontrolling signal SWDX=Vii (“H” level). Therefore, the driving signalSWL=Vnwl. Here, symbol Vii represents the voltage of the step-down powersource in the DRAM, and represents the “H” level which is lower than the“H” level of the step-up voltage Vpp.

Next, when the memory cell starts the active operation and enters theactivated state, the memory cell is driven in such a manner that thelevel of the signal at the node n01 becomes equal to the negativevoltage Vnwl and the level of the high voltage side power source voltageSWDZ reaches the step-up voltage Vpp. Further, the memory cell iscontrolled at the same timing so that the reset control signal SWDXbecomes equal to Vnwl. Since the level of the selection signal MWL isset to the negative voltage Vnwl, the driving signal rises up to thestep-up voltage Vpp.

The reset operation of the word line is executed when the activatedstate of the memory cell is returned to the standby state. In this case,the node n01 is first raised to the step-up voltage, so that the levelof the high voltage side power source signal SWDZ reaches the voltageVnwl. Since the level of the selection signal MWL remains the negativevoltage Vnwl at this time, the P-channel transistor 285 becomesoperative and the source of this transistor is connected to the nodeSWL. In consequence, the charges that are stored in the word line areabsorbed by the negative power source through the P-channel transistor285, and the potential of the node (word line) outputting the drivingsignal SWL drops. As the potential of this node lowers, the voltagecomes close to the threshold voltage of the P-channel transistor 285.Therefore, a control is carried out at a suitable timing so that theselection signal MWL=Vpp. Furthermore, the node outputting the drivingsignal SWL is reset through the N-channel transistor 290 and is clampedat the negative voltage Vnwl. The negative voltage Vnwl clamped in thisway corresponds to the reset potential of the word line.

In this case, all the charges Q (Q=(Vpp−Vnwl)×Cswl) charged to the nodeoutputting the driving signal SWL must be absorbed by the negative powersource having the negative voltage Vnwl. Here, symbol Cswl representsthe total capacitance of the node.

The negative potential that is used for the reset operation of the wordline and corresponds to the negative voltage Vnwl is not applied fromoutside the DRAM, and must be generated in the DRAM. A circuit thatcomprises an oscillating circuit unit and a pumping circuit unit isgenerally known as a negative potential generating circuit forgenerating such a negative potential.

Therefore, the construction of the semiconductor device according to theprior art, that absorbs the charge of the word line that is charged tothe step-up voltage, under the activated state of the cell transistor,by the negative voltage, involves the problem that more power isconsumed than in the construction in which the word line charge isabsorbed by the power source of the ground potential. On the other hand,it is essentially necessary to set the potential at the time of thereset operation of the word line to a voltage level, which is as low aspossible, in order to minimize the leak of the charge stored in the cellcapacitor.

On the other hand, an increase in the refresh current causes adeterioration of a performance of the DRAM. To solve this disadvantage,Japanese Unexamined Patent Publication (Kokai) No. 9-134591 discloses aconstruction that reduces the sub-threshold leak by setting thepotential of the non-selected word line (reset potential) to thenegative potential below the ground level. FIG. 3 shows the basicconstruction of the semiconductor device as the second example of theprior art such as the device of Japanese Unexamined Patent Publication(Kokai) No. 9-134591. In addition to the conventional constructionincluding the memory cell array, the word line driver (word line drivercircuit) 200 and the X decoder (row decoder, that is, word line decoder)300, a WL (word line) reset level generating circuit 400 is disposed sothat the negative potential generated by this circuit 400 is supplied tothe word line driver (word line driver circuit) 200.

The source and the drain of the cell transistor are connected to one ofthe ends of the capacitance and to the bit line, respectively. However,when the circuit is designed in such a manner that the potentials of thesource and the drain do not fall to a level below the ground level, anegative bias voltage is applied between the gate and the source of thenon-selected transistors if the potential of the word line connected tothe gate of the cell transistor is lowered below the ground level. Thelarger becomes the negative value of the potential difference betweenthe gate and the source of the transistor, the smaller becomes thesub-threshold leak of the transistor in a form of an exponentialfunction, so that the decrease in the stored charges due to the leakagecurrent can be reduced. Therefore, the reduction of the leakage currentimproves stability and reliability of the memory operation andaccomplishes the improvement of performance such as the reduction ofconsumed power.

The negative potential generating circuit used in the second example ofthe conventional semiconductor devices allows the substrate potential ofthe cell transistor and its current supply/current absorption capabilityto be at a level that can sufficiently supplement the junction leak ofthe corresponding transistor. When the reset potential of the word lineis set to the negative potential, however, a load such as the word lineis charged and discharged by the negative potential power source.Therefore, a current supply capacity greater than that of the prior artdevices becomes necessary. Japanese Unexamined Patent Publication(Kokai) No. 9-134591 discloses merely the disposition of the negativepotential generating circuit but does not mention its construction,current supply capacity and current supplying method. However, it isassumed that the negative potential generating circuit that is disclosedin this reference quite naturally has a large current supply capacity.

When the negative potential generating circuit has a large currentsupply capacity, the power consumed in the negative potential generatingcircuit becomes great, too. Because the reduction of consumed power hasbeen required for the semiconductor devices, the reduction of consumedpower in the negative potential generating circuit is also required.

On the other hand, in order to cope with the disadvantage in which theoperation of the semiconductor device becomes unstable due to loweringof the driving voltage, Japanese Unexamined Patent Publication (Kokai)No. 2-73593 discloses the construction for improving stability of theoperation by increasing the voltage of the selected word line to a levelhigher than the voltage of the internal power source (internal voltage)and the power source voltage inputted from outside (external voltage).The aforementioned Japanese Unexamined Patent Publication (Kokai) No.9-134591 discloses the construction for reducing the sub-threshold leakby setting the potential of the non-selected word lines (resetpotential) to the negative potential below the ground level. Since theleak of the charges retained in the memory cell can be reduced in thisway, the refresh cycle can be extended and consumed power can bereduced, as well.

FIG. 4 shows the voltage (potential) levels generated in the DRAM. Thedrawing shows the power source voltage levels generated on the chip withrespect to the external power sources Vdd and GND, and these voltagelevels are generated by the power source circuit that drives thecapacitor by the oscillation signal. Symbol Vpp represents the “H” levelof the selected word line, Vnwl represents the word line reset level,Vbb represents the back-bias voltage of the cell transistor and Vpprrepresents the step-up potential (i.e., step-up voltage) for generatingVg. Symbol Vg represents a constant potential used as the gate potentialwhen the internally regulated voltage V2 is generated by using theN-channel transistor, as will be described later. Since Vg is V2+Vth(threshold voltage of the transistor), there is the case in whichVg>Vdd. Therefore, It is necessary to generate Vg from a potentialhigher than Vdd.

The negative potential Vbb is applied as the back-bias to the celltransistor so as (1) to prevent the forward-bias of the p-n junctioninside the chip and to prevent also the destruction of the data andlatch-up, (2) to reduce the change of the threshold voltage of the MOStransistor, (3) to reduce the junction capacitance by the back-bias(i.e., reverse-bias), and (4) to improve the transistor characteristicsby increasing the threshold voltage of a parasitic MOS transistor.

The “H” level (Vpp) of the selected word line must be set to a levelhigher than “H” level of the cell stored charge+Vth.

Recently, the requirement for lowering the Vpp level has arisen with theprogress of the lower voltage of the power source and lower powerconsumption of the semiconductor devices. To satisfy this requirement,the threshold voltage of the cell transistor must be lowered. When thethreshold voltage of the cell transistor is lowered, however, theleakage current increases at the OFF time of the cell transistor and theholding time of the charge stored in the cell drops, so that the stableand reliable operation is impeded. To cope with the problem of loweringof the threshold voltage of the cell transistor, Japanese UnexaminedPatent Publication (Kokai) No. 9-134591 proposes to set the word linereset level to the negative potential (Vnwl). If the word line resetlevel is kept at a potential lower than “L (Low)” of the bit lineamplification, the negative bias is always applied between the gate andthe source of the non-selected cell transistors in all the operatingconditions, and the leakage current of the non-selected cell transistorscan be thus reduced. In this way, a DRAM having high reliability can beaccomplished.

As described above, various voltages are used in the DRAM other than thepower source voltage supplied from external, and as to the power sourcevoltage described above, power source circuits for generating differentpotentials by driving the capacitor with the oscillation signal areused.

FIG. 5 shows a structural example of the power source circuits in theconventional DRAM described above. As shown in the drawing, a pluralityof power source circuits 10-0 to 10-n are provided on the chip. Eachpower source circuit includes an oscillation circuit 210 to 210-n acapacitor drive circuit 230 to 230-n a capacitor (pumping capacitor) 240to 240-n and an output circuit (output transistor) 250 to 250-n andoutputs a voltage Vp1 to Vpn different from the external power sourcevoltage.

The reduction of the chip area has been required for semiconductordevices so as to reduce the production cost. Also, the reduction ofpower consumption has been required to improve the chip performance (orchip characteristics). The semiconductor device includes a large numberof power source circuits as shown in FIG. 5 in order to improveperformance such as the high operation speed and the extension of therefresh time. From another aspect, however, this circuit constructioninvites the drop of performance such as the increase of the chip areaand the increase of power consumption. It is therefore indispensable toreduce as much as possible a deterioration of performance in anotheraspect with the improvement of performance such as the high operationspeed and the extension of the refresh time.

SUMMARY OF THE INVENTION

In view of the problems described above, it is the first object of thepresent invention to provide a semiconductor device which can minimizean increase of power consumption even when a word line is set to anegative potential for resetting the word line.

It is the second object of the present invention to reduce powerconsumption of a semiconductor device equipped with a negative potentialgenerating circuit for generating the potential which set the resetpotential of the word line to the negative potential.

It is the third object of the present invention to reduce the increaseof a chip area and power consumption in a semiconductor device equippedwith a plurality of power source circuits for improving performance suchas a high operation speed and the extension of a refresh time.

To accomplish the first object, the semiconductor device according tothe present invention includes a word line driver (word line drivecircuit) having the function of driving a word line connected to aspecific memory cell inside a memory cell array having a plurality ofmemory cells and for resetting the word line when the specific memorycell is returned from an activated state to a standby state, wherein thereset level of the word line driver, which is set when the resetoperation of the word line is executed, is switched between first andsecond potentials.

Preferably, in the semiconductor device according to the presentinvention, a reset level switch circuit unit for switching the resetlevel between the first and second potentials is disposed in the wordline driver.

Preferably, further, in the semiconductor device according to thepresent invention, a reset level switch circuit for switching the resetlevel between the first and second potentials is disposed separatelyfrom the word line driver.

Preferably, further, the semiconductor device according to the presentinvention includes further a plurality of word line drivers having thefunction of driving the word line connected to a specific memory cellinside a memory cell array having a plurality of memory cells and forresetting the word line when the specific memory cell is returned froman activated state to a standby state, and a reset level switch circuitfor switching the reset level of a plurality of word line driversbetween the first and second potentials is disposed separately from aplurality of word line drivers (a plurality of word line drive circuits)so that the switching operation of the reset level between the first andsecond potentials can be executed collectively by the reset level switchcircuit for these word line drivers.

Preferably, further, in the semiconductor device according to thepresent invention, the second potential is set to a level lower than thefirst potential.

Preferably, further, in the semiconductor device according to thepresent invention, the first potential of the reset level is the groundpotential and the second potential is a potential of a negative voltagelevel.

Preferably, further, in the semiconductor device according to thepresent invention, switching of the reset level to the first potentialis executed before the reset operation of the word line is started.

Preferably, further, in the semiconductor device according to thepresent invention, switching of the reset level to the second potentialis executed after the reset operation is started and the level of theword line drops.

Preferably, further, the semiconductor device according to the presentinvention includes a reset level switching control circuit for settingin advance a period, in which the level of the word line drops to apredetermined level from the start of the reset operation, and forswitching the reset level between the first and second potentials afterthis period passes from the timing of the start of the reset operation.

Preferably, further, the semiconductor device according to the presentinvention includes a word line potential judging circuit for supervisingthe potential of the word line, and for switching the reset levelbetween the first and second potentials when it detects the drop of thepotential of the word line to a level below a predetermined level.

Preferably, further, in the semiconductor device according to thepresent invention, the switching operation of the reset level betweenthe first and second potentials is executed by using an activationsignal and a non-activation signal for activating and non-activating asense amplifier provided to the memory cell array.

The aforementioned problem that power consumption increases in thesemiconductor device results presumably from the fact that the chargesof the “H” level, particularly the charges that are charged to the levelof the boosting voltage, are all absorbed by the negative power sourceas the voltage-generating power source in the semiconductor device.

In the semiconductor device according to the present invention,therefore, the charges that are charged to the “H” level are absorbed bythe power source of the first potential (ground potential, for example)in the first period of the reset operation of the word line, and afterthe level of the word line drops sufficiently, the remaining charges areabsorbed by the power source having the second potential (potential of anegative voltage level, for example) lower than the first potential.

According to this circuit construction, the major proportion of thecharges of the node of the word line, that are charged to the “H” level,are allowed to escape to the power source of the ground potential beforethe reset operation of the word line is started, and the amount of thecharges that are allowed to escape to the negative power source havinglow power source efficiency can be decreased drastically. In this way,the present invention can reduce power consumption in the semiconductordevice much more than the prior art devices, and can thus accomplish thefirst object described above.

To accomplish the second object, on the other hand, the semiconductordevice according to the present invention uses a word line reset levelgenerating circuit capable of varying the amount of a current supply ofthe negative potential, and changes the supply amount of the negativepotential in accordance with the operating condition of the memory cellarray.

In other words, the semiconductor device according to the presentinvention includes a plurality of word lines disposed in parallel, aplurality of bit lines extending in a vertical direction to theextending direction of the word lines, memory cell arrays each havingmemory cells that are disposed in the array form in such a manner as tocorrespond to a plurality word lines and to a plurality of bit lines,are connected to corresponding ones of these word lines and bit lines,and hold data by retaining the charge, and a word line reset levelgenerating circuit, wherein, when the non-selected word lines are set tothe negative potential by applying the output of the word line resetlevel generating circuit to the non-selected word lines, this word linereset level generating circuit can vary the amount of the current supplyof the negative potential, and varies the amount of the current supplyof the negative potential in accordance with the operating conditions ofthe memory cell array.

Preferably, the semiconductor device according to the present inventionfurther includes a word line reset level detecting circuit for detectingthe output state of the word line reset level generating circuit; and aword line reset level control circuit for controlling the operation ofthe word line reset level generating circuit on the basis of thedetection result of this reset level detecting circuit.

Preferably, further, in the semiconductor device according to thepresent invention, the word line reset level control circuit stops theoperation of the word line reset level generating circuit when thepotential of the word line reset level is below a first predeterminedvoltage, operates the word line reset level generating circuit so thatthe amount of the current supply of the word line reset level generatingcircuit becomes maximal when the potential of the word line reset levelgenerating circuit is above a second predetermined voltage, and controlsthe amount of the current supply of the word line reset level generatingcircuit in accordance with the access operation to the memory cell arraywhen the potential of the word line reset level is between the first andsecond predetermined voltages.

Preferably, further, when the semiconductor device according to thepresent invention comprises a plurality of banks, the word line resetlevel generating circuit comprises a plurality of circuit unitscorresponding to a plurality of banks and capable of operatingindependently, and these circuit units are selected and operated inaccordance with the operation of the memory cell array.

Preferably, further, in the semiconductor device according to thepresent invention, the word line reset level generating circuit includesan oscillation circuit, a capacitor and a capacitor drive circuit fordriving the capacitor, wherein a higher potential of a power source ofthe capacitor drive circuit is higher than a higher potential of a powersource of the oscillation circuit.

Preferably, further, in the semiconductor device according to thepresent invention, the word line reset level generating circuit includesan oscillation circuit, a capacitor and a capacitor drive circuit fordriving the capacitor, wherein the higher potential of power source ofthe capacitor drive circuit is equal to the higher potential of thepower source of the oscillation circuit.

Preferably, further, in the semiconductor device according to thepresent invention, the word line reset level generating circuit includesan oscillation circuit, a capacitor and a capacitor drive circuit fordriving the capacitor, wherein the higher potential of the power sourceof the capacitor drive circuit is lower than the higher potential of thepower source of the oscillation circuit.

Preferably, further, in the semiconductor device according to thepresent invention, the word line reset level generating circuit includesan oscillation circuit, a capacitor, a capacitor drive circuit fordriving the capacitor, and a power source switch circuit for switchingthe connection of a power source line of higher potential of thecapacitor drive circuit among the power source lines having a pluralityof different potentials.

Preferably, further, in the semiconductor device according to thepresent invention, the power source switch circuit executes theswitching operation between the power source line having a potentialhigher than the higher potential of the power source of the oscillationcircuit and the power source line of higher potential having a potentialequal to the potential of the oscillation circuit.

Preferably, further, in the semiconductor device according to thepresent invention, the power source switch circuit executes theswitching operation between the power source line having a potentialequal to the higher potential of the power source of the oscillationcircuit and the power source line having a potential lower than thehigher potential of the power source of the oscillation circuit.

Preferably, further, in the semiconductor device according to thepresent invention, the word line reset level generating circuit includesan oscillation circuit, a capacitor and a capacitor drive circuit fordriving the capacitor, wherein the capacitor drive circuit applies asingle oscillation signal outputted from the oscillation circuit to thecapacitor.

Preferably, further, in the semiconductor device according to thepresent invention, the word line reset level generating circuit includesan oscillation circuit, a capacitor and a capacitor drive circuit fordriving the capacitor, wherein the capacitor drive circuit applies aplurality of oscillation signals outputted from the oscillation circuitto the capacitor.

Preferably, further, in the semiconductor device according to thepresent invention, the word line reset level generating circuit includesa plurality of oscillation circuits for outputting oscillation signalshaving different frequencies, a capacitor, a capacitor drive circuit fordriving the capacitor, and a selection circuit for selecting theoscillation signal from a plurality of oscillation circuits to beapplied to the capacitor drive circuit.

Preferably, further, in the semiconductor device according to thepresent invention, the word line reset level generating circuit includesa plurality of oscillation circuits for outputting oscillation signalshaving different frequencies, a capacitor, a power source switch circuitfor switching the connection of a power source line of higher potentialof a capacitor drive circuit for driving the capacitor among a pluralityof power source lines having different potentials, and a selectioncircuit for selecting the oscillation signal from a plurality ofoscillation circuits to be supplied to the capacitor drive circuit.

Preferably, further, in the semiconductor device according to thepresent invention, the word line reset level generating circuit includesan oscillation circuit, a plurality of capacitor units, a plurality ofcapacitor drive circuit units for driving the capacitor units and aswitch for switching the input of the oscillation signal outputted fromthe oscillation circuit to each capacitor drive circuit unit, and thisswitch is switched in accordance with the operation of the memory cellarray.

Preferably, further, the semiconductor device according to the presentinvention includes an internal regulator circuit for down-converting thepower source voltage supplied from outside, and the higher potential ofthe power source of the oscillation circuit is supplied from thisinternal regulator circuit.

Generally, when the word line which is selected and activated is reset,a large current flows to the word line reset level and for this reason,a current supply of this circuit must be increased. When thesemiconductor device is in a standby state, on the contrary, thiscircuit may have a current supply capacity sufficient to supply acurrent necessary for keeping the reset level. In the semiconductordevice according to the present invention, therefore, the supply amountof the word line reset level generating circuit is increased when alarge current supply capacity is required, and is decreased when a smallcurrent supply capacity may suffice. Consequently, if the word linereset level is set to the negative potential, then power consumption ofthe word line reset level generating circuit can be reduced. In thisway, the second object of the present invention can be accomplished.

To accomplish the third object, the semiconductor device according tothe present invention uses in common the oscillation circuit for aplurality of power source circuits.

In other words, the semiconductor device according to the presentinvention includes a plurality of power source circuits, each includingan oscillation circuit and a capacitor, for generating a differentpotential by driving the capacitor by the oscillation signal outputtedby the oscillation circuit, wherein at least a part of a plurality ofpower source circuits shares in common the oscillation circuit, anddifferent capacitors are driven by the oscillation signal outputted fromthe common oscillation circuit.

Preferably, in the semiconductor device according to the presentinvention, each power source circuit is equipped with an operationcontrol circuit at the input portion of the oscillation signal outputtedfrom the common oscillation circuit to the capacitor drive circuit.

Preferably, further, in the semiconductor device according to thepresent invention, the power source circuits sharing the oscillationcircuit generate different potentials.

Preferably, further, in the semiconductor device according to thepresent invention, the common oscillation circuit outputs a plurality ofoscillation signals having different phases, and the capacitor is drivenby a plurality of oscillation signals having different phases.

Preferably, further, in the semiconductor device according to thepresent invention, the power source circuits, having the capacitor thatis driven by a plurality of oscillation signals having different phases,generate the same potential, and the outputs of the power sourcecircuits are connected in common.

Preferably, further, in the semiconductor device according to thepresent invention, the power source circuit includes an operationcontrol circuit disposed at the input portion of the oscillation signaloutputted from the common oscillation circuit to the capacitor drivecircuit, and switching the operating state of the power source circuitbetween the operating state and the non-operating state, and a potentialdetecting circuit for detecting the potential generated by the powersource circuit, wherein the operation control circuit is controlled onthe basis of the detection result of the potential detecting circuit.

Preferably, further, the semiconductor device according to the presentinvention includes a plurality of power source circuits each including aclock input circuit for receiving the clock inputted from outside and acapacitor, for generating different potentials by driving the capacitorby an internal clock for power source outputted by the clock inputcircuit,

Preferably, in the semiconductor device according to the presentinvention, the clock input circuit includes a frequency dividing circuitfor frequency-dividing the clock, and the output of the frequencydividing circuit is outputted as the internal clock for power source.

Because the semiconductor device according to the present invention usesin common the oscillation circuit that has been provided in the past toeach of a plurality of power source circuits, the semiconductor deviceof the present invention can eliminate the overlapping oscillationcircuits and consequently, can reduce the chip area and powerconsumption of the overlapping oscillation circuits.

Because the operation control circuit is provided to the input portionof the oscillation signal outputted from the common oscillation circuitto the capacitor drive circuit, the operating condition can becontrolled and in this way, the third object of the present inventioncan be accomplished.

Furthermore, the power source circuits sharing in common the oscillationcircuit may generate different potentials or the same potential. Whenthe same potential is generated, the outputs of the power sourcecircuits are connected and used.

The capacitor may be driven by the oscillation signal having the samephase or by a plurality of oscillation signals having different phases.When the outputs of the power source circuits for generating the samepotential are connected, the efficiency does not drop, even when thecycle of the oscillation signal is shortened, if the capacitors of thepower source circuits are driven by a plurality of oscillation signalshaving different phases.

Furthermore, stable supply of the power source becomes possible byproviding the operation control circuit to the input portion of thecapacitor drive circuit and providing the potential detecting circuitfor detecting the potential generated by the power source circuit, andby controlling the operation control circuit on the basis of thedetection result of the potential detecting circuit.

Incidentally, it is possible to receive the clock inputted from outsideby the clock input circuit and to drive the capacitors of a plurality ofpower source circuits for generating different potentials, by the outputof the clock input circuit. The voltage can be stepped down similarly.In this case, the frequency dividing circuit for frequency-dividing theclock is provided in the clock input circuit so as to use the clockhaving a suitable cycle for the power source circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and features of the present invention will be moreapparent from the following description of the preferred embodimentswith reference to the accompanying drawings, wherein:

FIG. 1 is a circuit diagram showing the first example of theconstruction of a semiconductor device having a function of setting areset potential to a negative potential according to the prior art;

FIG. 2 is a timing chart useful for explaining the operation of theprior art device shown in FIG. 1;

FIG. 3 is a schematic view showing the second example of the basicconstruction of a DRAM for setting the reset level of a word line to anegative level according to the prior art;

FIG. 4 is a diagram showing the voltage levels used in the DRAM;

FIG. 5 is a circuit diagram showing a structural example of a powersource circuit according to a prior art example;

FIG. 6 is a circuit diagram showing the construction of the firstembodiment of the present invention;

FIG. 7 is a timing chart useful for explaining the operation of theembodiment shown in FIG. 6;

FIG. 8 is a circuit diagram showing the construction of the secondembodiment of the present invention;

FIG. 9 is a circuit diagram showing the detailed construction of a resetpotential generating circuit in the embodiment shown in FIG. 8;

FIG. 10 is a timing chart useful for explaining the operation of theembodiment shown in FIG. 8;

FIG. 11 is a circuit diagram showing the detailed construction of anegative potential generating circuit used in the embodiment of thepresent invention;

FIG. 12 is a timing chart useful for explaining the operation of thenegative potential generating circuit shown in FIG. 11;

FIG. 13 is a plan view showing the schematic construction of asemiconductor memory used in the embodiment of the present invention;

FIG. 14 is a block circuit diagram showing the construction of principalportions of a semiconductor memory according to the first embodiment ofthe present invention;

FIG. 15 is a block circuit diagram showing the construction of principalportions of a semiconductor memory according to the second embodiment ofthe present invention;

FIG. 16 is a block circuit diagram showing the construction of principalportions of a semiconductor memory according to the third embodiment ofthe present invention;

FIG. 17 is a block circuit diagram showing the construction of a resetlevel switching control timing circuit used in the embodiment of thepresent invention; FIG. 18 is a timing chart useful for explaining theoperation of the reset level switching control timing circuit shown inFIG. 17;

FIG. 19 is a block circuit diagram showing the construction of a wordline potential judging circuit used in the embodiment of the presentinvention;

FIG. 20 is a timing chart useful for explaining the operation of theword line potential judging circuit shown in FIG. 19;

FIG. 21 is a block diagram showing the construction of a basicembodiment on the basis of the basic principle for accomplishing thesecond object;

FIG. 22 is a block diagram showing the bank construction of a DRAMaccording to the fourth embodiment of the present invention;

FIG. 23 is a block diagram showing the construction of the DRAMaccording to the fourth embodiment;

FIG. 24 is a block diagram showing the construction relating to thegeneration and control of a WL reset level in the fourth embodiment;

FIG. 25 is a block diagram showing the construction of a WL reset levelgenerating circuit in the fourth embodiment;

FIGS. 26A and 26B are circuit diagrams each showing a structural exampleof an internal regulator circuit;

FIG. 27 is a circuit diagram showing a concrete structural example ofthe WL reset level generating circuit of the fourth embodiment;

FIG. 28 is a circuit diagram showing another structural example of theWL reset level generating circuit of the fourth embodiment;

FIG. 29 is a circuit diagram showing another structural example of theWL reset level generating circuit of the fourth embodiment;

FIGS. 30A, 30B, 30C and 30D are circuit diagrams each showing astructural example of a WL reset level detecting circuit;

FIG. 31 is a circuit diagram showing the construction of the reset levelcontrol circuit of the fourth embodiment;

FIG. 32 is a timing chart useful for explaining a reset levelcontrolling method in the fourth embodiment;

FIG. 33 is a circuit diagram showing the construction of a row decoderand a WL driver in the fourth embodiment;

FIG. 34 is a timing chart (when one bank operates) showing the levelchange of the word line and the bit line in the fourth embodiment;

FIG. 35 is a timing chart (when two banks operate) showing the levelchange of the word line and the bit line in the fourth embodiment;

FIG. 36 is a timing chart (when four banks operate) showing the levelchange of the word line and the bit line in the fourth embodiment;

FIG. 37 is a block circuit diagram showing the basic construction of aWL reset level generating circuit in a modified embodiment of the fourthembodiment;

FIG. 38 is a circuit diagram showing the construction of the WL resetlevel generating circuit of the modified embodiment of the fourthembodiment;

FIG. 39 is a block circuit diagram showing the construction relating tothe generation and control of the WL reset level in the fifth embodimentof the present invention;

FIGS. 40A and 40B are circuit diagrams each showing a structural exampleof the WL reset level detecting circuit of the fifth embodiment;

FIGS. 41A and 41B are circuit diagrams each showing another structuralexample of the WL reset level detecting circuit of the fifth embodiment;

FIG. 42 is a block circuit diagram showing the basic construction of theWL reset level generating circuit of the sixth embodiment of the presentinvention;

FIGS. 43A and 43B are diagrams showing the construction and operation ofthe WL reset level generating circuit in the sixth embodiment;

FIG. 44 is a block circuit diagram showing the basic construction of theWL reset level generating circuit in the seventh embodiment of thepresent invention;

FIG. 45 is a circuit diagram showing the construction of the WL resetlevel generating circuit of the seventh embodiment;

FIG. 46 is a timing chart showing the operation of the WL reset levelgenerating circuit in the seventh embodiment;

FIG. 47 is a block circuit diagram showing the operation of the WL resetlevel generating circuit in the eighth embodiment;

FIG. 48 is a circuit diagram showing the construction of the WL resetlevel generating circuit of the eighth embodiment;

FIG. 49 is a timing chart showing the operation of the WL reset levelgenerating circuit of the eighth embodiment;

FIG. 50 is a block circuit diagram showing the basic construction of theWL reset level generating circuit of the ninth embodiment;

FIG. 51 is a circuit diagram showing the construction of the WL resetlevel generating circuit of the ninth embodiment;

FIG. 52 is a timing chart showing the operation of the WL reset levelgenerating circuit in the ninth embodiment;

FIGS. 53A and 53B are a circuit diagram and a timing chart showing theconstruction and operation of the WL reset level generating circuit ofthe modified embodiment of the ninth embodiment;

FIG. 54 is a schematic view showing the bank construction of the DRAM inthe tenth embodiment;

FIG. 55 is a block diagram showing the DRAM in the tenth embodiment;

FIG. 56 is a block diagram showing the basic construction of the powersource circuit in the tenth embodiment;

FIGS. 57A and 57B are circuit diagrams each showing a structural exampleof an internal regulator source circuit;

FIG. 58 is a circuit diagram showing the concrete construction of thepower source circuit of the tenth embodiment;

FIG. 59 is a circuit diagram showing the concrete construction of thepower source circuit of the tenth embodiment;

FIG. 60 is a circuit diagram showing another structural example of abooster circuit of the tenth embodiment;

FIG. 61 is block circuit diagram showing the basic construction of thepower source circuit in the eleventh embodiment;

FIG. 62 is a block diagram showing the construction of a semiconductordevice according to the twelfth embodiment; and

FIGS. 63A and 63B are circuit diagrams showing a structural example of afrequency-dividing circuit in the twelfth embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, the basic embodiment of the present invention and somepreferred embodiments thereof will be explained with reference to FIGS.6 to 63B of the accompanying drawings.

Initially, a preferred embodiment for accomplishing the first object ofthe present invention will be explained.

FIG. 6 is a circuit diagram showing the construction of the firstembodiment of the present invention, and FIG. 7 is a timing chart usefulfor explaining the operation of the embodiment shown in FIG. 6. In thiscase, too, however, the circuit construction fbr driving the word linein the semiconductor device is shown in the drawings so as to simplifythe explanation.

In the first embodiment shown in FIG. 6, there is disposed a word linedrive circuit 2 for supplying a drive signal SWL of a predeterminedvoltage level to the word line connected to the gate of the celltransistor in the memory cell. This word line drive circuit 2 includesan inverter, that comprises a P-channel transistor 21 and an N-channeltransistor 22 and outputs the drive signal SWL on the basis of theselection signal MWL, and an N-channel transistor 23 for clamping theword line at a reset potential on the basis of a reset control signalSWDX.

The P-channel transistor 21, the N-channel transistor 22 and theN-channel transistor 23 inside the word line drive circuit 2substantially correspond to the P-channel transistor 285, the N-channeltransistor 290 and the N-channel transistor 295 of the word line drivecircuit 280 according to the prior art example (shown in FIG. 1),respectively.

The embodiment shown in FIG. 6 includes further a word line drivecontrol circuit 1 for controlling the voltage level of the drive signalSWL by supplying the high voltage side power source signal SWDZ to thesource of the P-channel transistor 21 of the word line drive circuit 2.This word line drive control circuit 1 includes an inverter comprising aP-channel transistor 11 and an N-channel transistor 12. The source ofthe P-channel transistor 11 is connected to a power source of a boostingvoltage Vpp (step-up power source) while the source of the N-channeltransistor 12 is connected to a negative power source of a negativevoltage Vnwl. Here, the step-up voltage Vpp or the high voltage sidepower source signal SWDZ of the negative voltage Vnwl is supplied to thehigh voltage side power source of the word line drive circuit 2 on thebasis of the control signal inputted from a node n01 on the input sideof the inverter.

The P-channel transistor 11 and the N-channel transistor 12 in the wordline drive circuit 1 substantially correspond to the P-channeltransistor 170 and the N-channel transistor 175 in the word line drivecontrol circuit 180 of the aforementioned prior art example (shown inFIG. 1), respectively.

In the embodiment shown in FIG. 6, further, a reset level switch circuitunit 3 for switching a potential of the ground level Vss of the resetlevel and a potential of the negative voltage Vnwl (that is, switchingof the reset potential) is disposed in the word line drive circuit 2.This reset level switch circuit unit 3 includes N-channel transistors 31and 32 for switching the potential of the source of the N-channeltransistor 22 connected to the node of the word line, between the groundvoltage Vss and the negative voltage Vnwl, and an inverter 33 connectedbetween the gate of the N-channel transistor 31 and the gate of theN-channel transistor 32. Further, the reset level switch circuit unit 3includes N-channel transistors 34 and 35 for switching the sourcepotential of the N-channel transistor 23 connected to the node of theword line, between the ground voltage Vss and the negative voltage Vnwl.

When the reset operation of the word line is executed, the level of thenode n03 of the N-channel transistor 22 of the word line drive circuit 2(that is, the reset level) is set to the potential of the ground voltageVss (the first potential), or to the potential of the negative voltageVnwl (the second potential) in accordance with the reset potentialswitch control signal supplied from the node n02 to the gates of theN-channel transistors 31 and 35. When the reset operation of the wordline is commenced, the control signal of the “L” level is first suppliedfrom the node n02. In consequence, the N-channel transistor 32 becomesoperative and the reset level reaches the potential of the groundvoltage Vss. After the level of the word line (that is, the level of thedrive signal SWL) sufficiently drops, the control signal of the “H”level is supplied from the node n02. Consequently, the N-channeltransistor 31 becomes operative and the reset level is switched to thepotential of the negative voltage VnWl.

The operation of the embodiment shown in FIG. 6 is illustrated in thetiming chart of FIG. 7. As can be seen clearly from FIG. 6, the signallevel at each of the nodes n01, n02 and n03 and at each portion is underthe following state when the memory cell is in a standby state, in thefirst place.

Signal level at the node n01=Vpp (“H” level), the signal level at thenode n02=Vii (“H” level), the high voltage side power source signalSWDZ=Vnwl (the low voltage level (“L” level) the selection signalMWL=Vpp, and the reset control signal SWDX=Vii (“H” level). Therefore,the drive signal SWL=Vnwl. Here, symbol Vii represents the voltage ofthe step-down power source inside the DRAM, as described already.

Next, when the memory cell starts the active operation and enters theactivated state, the memory cell is driven so that signal level at thenode n01 is equal to the negative voltage Vnwl and the level of the highvoltage side power source signal reaches the step-up voltage Vpp.Control is made at the same timing in such a fashion that the resetcontrol signal SWDX becomes equal to Vnwl. Furthermore, as the level ofthe selection signal MWL is set to the negative voltage Vnwl, the drivesignal SWL reaches the step-up voltage Vpp.

The reset operation of the word line is executed in order to return theactivated state of the memory cell to the stand by state. In this case,the reset operation of the word line is executed by setting theselection signal MWL to Vpp and extracting the charge, to the powersource of the ground voltage Vss, through the N-channel transistors 22and 32 of the word line drive circuit 2. At this time, the level of thesignal at the node n02 has already become the negative voltage Vnwl.Such a level change at the node n02 can be accomplished by executing thecontrol so that the word line potential reaches the step-up voltage Vppand the operation mode enters the activated state.

The charges that are charged to the word line are then absorbed by thepower source of the ground voltage Vss through the N-channel transistors22 and 32 of the word line drive circuit 2 (refer to the waveform of thedriving signal SWL). After the potential of the word line correspondingto the level of the drive signal SWL has sufficiently dropped, controlis made so that the potential of the node n02=“Vii”. The route of thecharge absorption is switched to the negative power source of thenegative voltage Vnwl by turning OFF the N-channel transistor 32 andturning On the N-channel transistor 31, and then the reset potential ofthe word line is clamped at the negative power source. The followingmethods may be employed as a method of bringing the potential of thenode n02 to “Vii” after the potential of the word line has sufficientlydropped; {circle around (1)} a method that simulates and controls thetime, in which the potential of the word line drops sufficiently, by atiming circuit, and {circle around (2)} a method that monitors the wordline potential in the semiconductor device and automatically changes thepotential of the node n02. Concrete circuit constructions foraccomplishing these controlling methods will be later described withreference to FIGS. 17 to 20.

As to the flow of the charges when the reset operation of the word lineis executed in the first embodiment described above, the charges flowfrom the word line→N-channel transistor 22→N-channel transistor 32→powersource of ground voltage Vss, at the start of the reset operation. Whenthe potential of the word line has sufficiently dropped, the chargesflow from the word line→N-channel transistor 22→N-channel transistor31→power source of negative voltage Vnwl. In other words, at the startof the reset operation of the word line, the major proportion of thecharges that the node of the word line hold are allowed to first escapeto the power source of the ground voltage Vss, and in this way, thequantity of the charges escaping to the negative power source having lowpower source efficiency decreases drastically. In consequence, powerconsumption in the semiconductor device can be drastically saved.

FIG. 8 is a circuit diagram showing the construction of the secondembodiment and FIG. 9 is a circuit diagram showing the detailedconstruction of a reset potential generating circuit in the embodimentshown in FIG. 8. FIG. 10 is a timing chart for explaining the operationof the embodiment shown in FIG. 8. In this case, too, the circuitconstruction for driving the word line inside the semiconductor deviceis shown in the drawings so as to simplify the explanation. Likereference numerals will be used hereinafter to identify like constituentelements described already.

In the second embodiment shown in FIG. 8, there is disposed a word linedrive circuit 2 a for supplying a drive signal SWL of a predeterminedvoltage level to the word line connected to the gate of the celltransistor inside the memory cell. This word line drive circuit 2 aincludes an inverter comprising a P-channel transistor 24 and anN-channel transistor 25, for outputting the drive signal SWL on thebasis of the selection signal MWL, and an N-channel transistor 26 forclamping the word line at a predetermined reset potential on the basisof the reset control signal SWDX. The sources of the N-channeltransistors 25 and 26 are connected to the power source of the negativevoltage Vnwl (negative power source) for resetting the word line.

The P-channel transistor 24, the N-channel transistor 25 and theN-channel transistor 26 inside the word line drive circuit 2 asubstantially correspond to the P-channel transistor 285, the N-channeltransistor 290 and the N-channel transistor 295 in the word line drivecircuit 280 of the prior art example (see Fig. respectively.

In the embodiment shown in FIG. 8, a word line drive controlling circuit1 is provided so as to control the voltage level of the drive signal SWLby supplying the high voltage side power source signal SWDZ to thesource of the P-channel transistor 24 of the word line drive circuit 2 ain the same way as in the first embodiment (see FIG. 6). This word linedrive control circuit 1 has an inverter comprising a P-channeltransistor 11 and an N-channel transistor 12 in the same way as in thefirst embodiment. The source of the P-channel transistor 11 is connectedto the power source of the step-up voltage (step-up power source) andthe source of the N-channel transistor 12 is connected to the outputterminal of the reset potential generating circuit 4. The reset powersource supply signal VRST is supplied from the output terminal of thisreset potential generating circuit 4 to the source of the N-channeltransistor 12.

In this case, the reset potential generating circuit 4 has the functionof a reset level switch circuit for switching the first and secondpotentials of the reset level of the word line drive circuit 2 a, and isdisposed separately from the word line drive circuit 2 a.

FIG. 9 shows the detailed construction of the reset potential generatingcircuit 4. Here, the reset potential generating circuit 4 includes twoN-channel transistors 41 and 42 and an inverter connected between thegate of one (41) of the N-channel transistors and the gate of the otherN-channel transistor 42. In order to execute the reset operation of theword line, the level of the reset power source supply signal VRST (thatis, the reset level) is set to the potential of the ground voltage Vssand to the potential of the negative voltage Vnwl in accordance with thereset potential switch control signal supplied from the node n02 to thegates of the N-channel transistors 41 and 42. When the reset operationof the word line is started, the control signal of the “L” level isfirst supplied from the node n02, so that the transistor 42 is ON andthe reset level reaches the potential of the ground voltage Vss. Afterthe level of the word line (that is, the level of the drive signal SWL)has sufficiently dropped, the control signal of the “H” level issupplied from the node n02. In consequence, the N-channel transistor 41is turned ON and the reset level is switched to the potential of thenegative voltage Vnwl.

The operation of the embodiment shown in FIGS. 8 and 9 is illustrated inthe timing chart of FIG. 10. As is obvious from FIG. 8, when the memorycell is in a standby state, the levels of the signals of the nodes n01and n02 and at each portion are as follows. The signal level at the noden01=Vpp (“H” level), the signal level at the node n02=Vii (“H” level),the high voltage side power source signal SWDZ=Vnwl (low voltage level(“L” level), the selection signal MWL=Vpp, and the reset control signalSWDX=Vii. Accordingly, the drive signal SWL=Vnwl.

Next, when the memory cell starts the active operation and enters theactivated state, the level of the signal at the node n01 is equal to thenegative voltage Vnwl and the level of the high voltage side powersource signal SWDZ reaches the step-up voltage Vpp. At the same timing,control is made so that the reset control signal SWDX is equal to Vnwl.Furthermore, as the level of the selection signal MWL is set to thenegative voltage Vnwl, the drive signal rises to the step-up voltageVpp.

The reset operation of the word line is executed when the activatedstate of the memory cell is returned to the standby state. In this case,the reset operation of the word line is executed by setting the level ofthe signal at the node n01 to the boosting voltage Vpp and by extractingthe charges to the power source of the ground voltage Vss inside thereset potential generating circuit 4 through the P-channel transistor 24of the word line drive circuit 2 a. By this time, the level of thesignal at the node n02 has already become the negative voltage Vnwl.Such a level change at the node n02 can be accomplished by executing thecontrol so that the potential of the word line rises to the step-upvoltage Vpp during the activated state.

In this way, the charges stored by the word line are absorbed by thepower source of the ground voltage Vss through the N-channel transistor12 of the word line drive controlling circuit 1 and through theN-channel transistor 42 of the reset potential generating circuit 4(refer to the waveform of the drive signal SWL). After the potential ofthe word line, that corresponds to the level of the drive signal SWL,has sufficiently dropped, the control is made so that the node n02becomes equal to “Vii”. The N-channel transistor 31 is turned OFF whilethe N-channel transistor 41 is turned ON, thereby switching the route ofcharge absorption to the negative power source having the negativevoltage Vnwl, and the reset potential of the word line is clamped at thenegative power source.

Since the P-channel transistor 24 of the word line drive circuit 2 a isinterposed into this route, the potential comes close to the thresholdvoltage of the P-channel transistor, and the charges cannot besufficiently absorbed by the negative power source of the negativevoltage Vnwl. To avoid such a problem, the selection signal MWL and thereset control signal SWDX are set to the “H” level at a suitable timing,and the reset potential of the word line is clamped to the negativepower source.

According to this circuit construction, the quantity of the charges Qthat must be absorbed by the negative power source (the negative voltageVnwl) during the reset operation of the word line becomes by far smaller[Q={(Vnwl+Vthp)−Vnwl}×Cswl]. Here, symbol Cswl represents the totalcapacitance of the nodes of the word line and symbol Vthp does thethreshold voltage between the gate and the source of the P-channeltransistor 24 of the word line drive circuit 2 a. In this case, thepotential of the source of the P-channel transistor 24 drops only toVnwl+Vthp.

The control methods for attaining the relation, i.e. node n02=“Vii”,after the potential of the word line has sufficiently dropped, may bethe same as those of the first embodiment, that is, {circle around (1)}the method that simulates and controls the time in which the word linepotential sufficiently drops, by a timing circuit, and {circle around(2)} the method that supervises the word line potential inside thesemiconductor device and automatically changes the potential of the noden02.

As to the flow of the charges when the reset operation of the word lineis carried out in the second embodiment described above, the chargesflow from the word line→P-channel transistor 24→N-channel transistor12→signal line of reset power source supply signal VRST→N-channeltransistor 42→ground voltage Vss, at the start of the reset operation.When the potential of the word line has sufficiently dropped, thecharges flow from the word line→P-channel transistor 24→N-channeltransistor 12→signal line of reset power source supply signalVRST→N-channel transistor 41→power source of negative voltage Vnwl.

In the first embodiment described above, the charges are directlyextracted from the word decoder comprising the word line drive circuitbut in this second embodiment, the charges are extracted through theP-channel transistor.

In the first embodiment described above, further, the reset level switchcircuit unit is disposed inside the word decoder but in this secondembodiment, only the reset level switch circuit (for example, the resetpotential generating circuit 4) is disposed independently of the worddecoder.

In the drawings of the word decoders in general, the width is determinedin such a manner as to correspond to the pitch of the word lineconnected to the memory cells. Therefore, the increase in the number ofconstituent elements such as the reset level switch circuit unit, etc,results in the increase of the length of the word decoder. Recently,methods that dispose a plurality of word decoders and divide the wordline into short segments have often been employed in order to reduce theinfluences of the resistance of the word line. Therefore, the increasein the number of devices that constitute the word decoder directlyresults in the increase in the chip area.

To solve such a problem, the second embodiment separates the reset levelswitch circuit from the word decoder portion having a large number oflimitations, disposes it at a portion having a small number oflimitations and thus prevents the increase of the area of thesemiconductor chip.

On the other hand, the non-activation signal of the sense amplifier canbe used for switching the reset level without using any specific controlsignal. The activation timing and the non-activation timing of the senseamplifier are as follows. Activation is effected when the word linerises, the charge stored in the cell capacitor propagates through thebit lines and a potential difference is generated between the bit linepair, whereas non-activation is effected when the re-write operation tothe memory cell is executed, the potential of the word line is loweredand the cell transistor enters the non-activated state. Therefore, theoperation timing of the control signal desired in the semiconductordevice according to the present invention coincides with the controltiming of the activation signal and the non-activation signal of theexisting sense amplifier. The increase in the number of the controlsignals results in an increase of the number of the control circuits andresults eventually and undesirably in an increase in consumed power dueto the circuit operations.

FIG. 11 is a circuit diagram showing the detailed construction of thenegative potential generating circuit used in the embodiment of thepresent invention, and FIG. 12 is a timing chart useful for explainingthe operation of the negative potential generating circuit shown in FIG.11.

A circuit comprising the oscillation circuit unit 5 a and the pumpcircuit unit 5 b and using the potential of the ground voltage Vss asthe reference, as shown in FIG. 11, is generally known as the negativepotential generating circuit used for switching the reset level to thenegative potential. The oscillation circuit unit 5 a is constituted byconnecting three inverters 50 to 52 in the ring form. The pump circuitunit 5 b includes a pumping capacitor 53 and two N-channel transistors54 and 55. The oscillation signal of the square wave outputted from theoscillation circuit unit 5 a has the negative potential which isgenerated by the pumping operation of the pumping capacitor 53 and theN-channel transistors 54 and 55.

The operation of the negative potential generating circuit of FIG. 11 isshown in FIG. 12. As is obvious from FIG. 12, the oscillation signal ofthe square wave having a voltage Vdd is outputted from the inverter 52(node A) of the last stage of the oscillation circuit unit 5 a. Further,a pulse-like voltage waveform containing three voltages, i.e. Vdd, VT1and −VT2, is obtained from the node B of the pumping capacitor 53. Thesethree voltages are overlapped with one another in accordance with thepumping operation by the N-channel transistors 54 and 55, and a negativepotential having a voltage level of −Vdd+VT1+VT2 is generated. Generallyspeaking, the negative power source generated by such a negativepotential generating circuit has low power source efficiency and largeconsumed power.

In the embodiment of the present invention, the major proportion of thecharges held by the node of the word line at the start of the resetoperation of the word line are first allowed to escape to the powersource of the ground voltage Vss, and consumed power is minimized bydecreasing drastically the quantity of the charges escaping to thenegative power source having low power source efficiency.

FIG. 13 is a plan view showing the schematic construction of thesemiconductor memory used in this embodiment of the present invention.As shown in FIG. 13, the semiconductor memory 6 such as the DRAMincludes a plurality of word lines 61 and a plurality of bit line pairs62 crossing orthogonally the word lines 61 that are disposed for thecell array 60 containing a plurality of memory cells disposed in matrix.A word decoder 63 comprising the word line drive circuit is connected toa plurality of word lines 61 and a sense amplifier 64 used during thedata read operation is connected to a plurality of bit line pairs 62. Adrive signal for bringing the selected memory cell into the activatedstate or for returning the activated state to the stand-by state issupplied from the word decoder 63 to a plurality of word lines.Recently, means for disposing a plurality of word decoders and dividingthe word lines into short segments has been employed in order to reduceinfluences of the resistance of the word lines.

FIG. 14 is a block circuit diagram showing the construction of theprincipal portions of the semiconductor memory according to the firstembodiment of the present invention. The drawing typically illustratesthe construction of the semiconductor memory formed by incorporating theword line drive controlling circuit 1, the word line drive circuit 2 andthe reset level switch circuit unit 3 shown in FIG. 6.

In the semiconductor memory according to the first embodiment shown inFIG. 14, a plurality of reset level switch circuit units 3-1 to 3-n(where n is an arbitrary positive number of 2 or more than 2) aredisposed inside a plurality of word decoders 2-1 to 2-n, respectively.In this case, one reset level switch circuit unit is provided to eachword decoder. Furthermore, a plurality of control circuits 1-1 to 1-nfor supplying the high voltage side power source signal of these worddecoders are disposed independently of a plurality of word decoders 2-1to 2-n. These control circuits 1-1 to 1-n are disposed at positions inwhich a plurality of word decoders 2-1 to 2-n and the sense amplifier 64are not disposed.

The construction of a plurality of word decoders 2-1 to 2-n (forexample, the first word decoder 2-1) in the semiconductor memory shownin FIG. 14 is the same as the construction of the word line drivecircuit 2 shown in FIG. 6. The explanation will be given in furtherdetail. The first decoder 2-1 includes an inverter circuit unitcomprising a P-channel transistor 21-1 and an N-channel transistor 22-1,for outputting the drive signal SWL on the basis of the selection signalMWL, and an N-channel transistor 23-1 for clamping the word line 61 atthe reset potential on the basis of the reset control signal SWDX.

In the semiconductor memory shown in FIG. 14, there is further disposeda first control circuit 1-1 for controlling the voltage level of thedrive signal SWL by supplying the high voltage side power source signalSWDZ to the source of the P-channel transistor 21-1 of the first worddecoder 2-1. This first control circuit 1-1 includes an invertercomprising a P-channel transistor 11-1 and an N-channel transistor 12-1.The source of the P-channel transistor 11-1 is connected to the powersource of the step-up voltage Vpp and the source of the N-channeltransistor 12-1 is connected to the negative power source having thenegative voltage Vnwl. Here, the step-up voltage Vpp or the high voltageside power source signal SWDZ of the negative voltage Vnwl is suppliedto the high voltage side power source of the first word decoder 2-1 onthe basis of the control signal inputted from the node n01 on the inputside of the inverter.

In the semiconductor memory shown in FIG. 14, a first reset level switchcircuit unit 3-1 for switching the potential of the ground voltage Vssof the reset level and the potential of the negative voltage Vnwl isdisposed inside the word line drive circuit 2 described above. Thisfirst reset level switch circuit unit 3-1 includes N-channel transistors31-1 and 32-1, that switch the source potential of the N-channeltransistor 22-1 connected to the node of the word line 61 between theground voltage Vss and the negative voltage Vnwl, and an inverter 33-1connected between the gate of the N-channel transistor 31-1 and the gateof the N-channel transistor 32-1. The first reset level switch circuit3-1 further includes N-channel transistors 34-1 and 35-1 for switchingthe source potential of the N-channel transistor 23-1 connected to thenode of the word line 61 between the ground voltage Vss and the negativevoltage Vnwl.

FIG. 15 is a block circuit diagram showing the construction of theprincipal portions of the semiconductor memory according to the secondembodiment of the present invention. The drawing typically illustratesthe construction of the semiconductor memory formed by incorporating theword line drive circuit 1, the word line drive circuit 2 a and the resetpotential generating circuit (that is, the reset level switch circuit)4.

In the semiconductor memory according to the second embodiment shown inFIG. 15, a plurality of reset potential generating circuits 4-1 to 4-n(where n is an arbitrary positive number of 2 or more than 2) areseparated from a plurality of word decoders 2 a-1 to 2 a-n, and they aredisposed at the same positions as those of a plurality of controlcircuits 1-1 to 1-n. In this case, too, each word decoder is providedwith one reset potential generating circuit, that is, the reset levelswitch circuit.

The construction of each of a plurality of word decoders 2 a-1 to 2 a-nin the semiconductor memory shown in FIG. 15 (for example, the firstword decoder 2 a-1) is the same as the construction of theaforementioned word line drive circuit 2 a shown in FIG. 8. Theexplanation will be given in further detail. The first word decoder 2a-1 includes an inverter comprising a P-channel transistor 24-1 and anN-channel transistor 25-1, for outputting the drive signal SWL on thebasis of the selection signal MWL, and an N-channel transistor 26-1 forclamping the word line at a predetermined reset potential on the basisof the reset control signal SWDX. The sources of these N-channeltransistors 25-1 and 26-1 are connected to the power source of thenegative voltage Vnwl for resetting the word line.

In the semiconductor memory shown in FIG. 15, there is further disposeda first control circuit 1-1 for controlling the voltage level of thedrive signal VWL by supplying the high voltage side power source signalSWDZ to the source of the P-channel transistor 24-1 of the first worddecoder 2 a-1, in the same way as in the case of FIG. 14. This firstcontrol circuit 1-1 includes an inverter comprising a P-channeltransistor 11-1 and an N-channel transistor 12-1 in the same way as inthe case of FIG. 14. The source of the P-channel transistor 12 1 isconnected to the output terminal of the first reset potential generatingcircuit 4-1. The reset power source signal VRST of the word line issupplied from the output terminal of this first reset potentialgenerating circuit 4-1 to the source of the N-channel transistor 12-1.

In this case, the first reset potential generating circuit 4-1 has thefunction of the reset level switch circuit that switches the reset levelof the first word decoder 2 a-1. The first reset potential generatingcircuit 4-1 is disposed separately from the first word decoder 2 a andat the same position as the position of the first reset potentialgenerating circuit 4-1.

FIG. 16 is a block circuit diagram showing the construction of theprincipal portions of the semiconductor memory according to the thirdembodiment of the present invention.

In the semiconductor memory according to the third embodiment shown inFIG. 16, a plurality of reset potential generating circuits (that is,the reset level switch circuits) 4 b-1 to 4 b-n/2 are separated from aplurality of word decoders 2 a-1 to 2 a-n, and they are disposed at thesame positions as the positions of a plurality of control circuits 1 b-1to 1 b-n/2. The basic construction and the operation are the same asthose of the semiconductor memory shown in FIG. 15. In this case,however, a plurality of word decoders of a certain unit (for example,two word decoders) share one reset level switch and execute,collectively, switching of the reset level by the reset level switchcircuits on the basis of the unit described above. Here, the selectionof the word decoders that share the switch circuit is made from otherseries by the selection signal MWL, or the like.

The construction of each word decoders 2 a-1 to 2 a-n in thesemiconductor memory shown in FIG. 16 (for example, the first worddecoder 2 a-1) is the same as the construction of the word decoder shownin FIG. 15.

Further, the construction of each of a plurality of control circuits 1b-1 to 1 b-n/2 is the same as the construction of the aforementionedcontrol circuit 1-1 shown in FIG. 10, and the construction of each of aplurality of reset level switch circuits 4 b-1 to 4 b-n/2 (for example,the first reset level switch circuit 4 b-1) is the same as theconstruction of the reset level switch circuit 4-1 shown in FIG. 15.Therefore, the detailed explanation of the word decoder, the controlcircuit and the reset level switch circuit will be hereby omitted.

In the semiconductor memory according to the third embodiment of thepresent invention, the switching operations of the reset level by thereset level switch circuits are collectively executed for a plurality ofword decoders. Therefore, the number of the reset level switch circuitscan be reduced and unnecessary power consumption can be restricted.

FIG. 17 is a block circuit diagram showing the construction of the resetlevel control timing circuit used in the embodiment of the presentinvention, and FIG. 18 is a timing chart useful for explaining theoperation of the reset level switch control timing circuit shown in FIG.17.

FIG. 17 shows the construction of the reset level switch control timingcircuit for executing a method which simulates and controls the periodin which the potential of the word line drops sufficiently, as the firstmethod of executing the control so as to attain the relation noden02=“Vii” at the time of the reset operation after the potential of theword line has sufficiently dropped. FIG. 18 shows the signal waveform ateach portion of the reset level switch control timing circuit shown inFIG. 17.

In FIG. 17, further, symbol RESET represents the signal that isoutputted when the semiconductor device receives the reset command,symbol RST represents the signal as a trigger for resetting the wordline drive circuit which is specifically handled in the presentinvention (for example, the select signal MWL in FIG. 6, and the signalat the node n01 in FIG. 8), and symbol SW represents the reset levelswitch signal. The reset level switch control timing circuit shown inFIG. 17 includes a logic unit 7 to which the signal RESET is inputted,and a control signal delay unit 8 which imparts a predetermined delay tothe control signal outputted from the node sw00 of this logic unit. Thiscontrol signal delay unit 8 imparts a desired delay amount to thecontrol signal by the combination of inverters 81 i to 84 i, capacitors81 to 83 and resistors 84 to 86.

As is obvious from the timing chart of FIG. 18, when the signal RESET isinputted to the logic unit 7 shown in FIG. 17, the logic unit 7 executesvarious logic operations and outputs the signal RST, so that the resetoperation of the word line is started. At the same time, the controlsignal is outputted from the node sw00 of the logic unit 7, which passesthrough the control signal delay unit 8 that is set in advance to theperiod in which the level of the word line sufficiently drops. Thecontrol signal propagating to the control signal delay unit 8 isoutputted as the switch signal SW of the reset level switch circuit. Theswitch signal SW outputted in this way is supplied as the resetpotential switch control signal to the node n02 shown in FIG. 6 or 8.

FIG. 19 is a block circuit diagram showing the construction of the wordline potential judging circuit used for the embodiment of the presentinvention, and FIG. 20 is a timing chart useful for explaining theoperation of the word line potential judging circuit shown in FIG. 19.

FIG. 19 shows the construction of the word line potential judgingcircuit for executing the method, that automatically changes thepotential of the node n02 by supervising the potential of the word linein the semiconductor device, as the second method for executing thecontrol so as to attain the relation node n02=“Vii” during the resetoperation of the word line after the potential of this word line hassufficiently dropped. FIG. 20 shows the signal waveform of each portionof the word line potential judging circuit shown in FIG. 19.

The word line potential judging circuit shown in FIG. 19 includes alogic unit 7 to which the signal RESET is inputted, a frequency dividingcircuit unit for frequency-dividing the control signal outputted fromthe node sw00 of this logic unit and obtaining a signal of apredetermined level, a resistor 92 as the reference of the potentialjudgement of the word line, three P-channel transistors 91, 93 and 95,and two N-channel transistors 94 and 96. The frequency dividing circuitunit includes four voltage-dividing resistors 74 to 77, a P-channeltransistor 72, an N-channel transistor 73, and an inverter 71 interposedbetween the gate of the P-channel transistor 72 and the gate of theN-channel transistor 73.

As is obvious from the timing chart of FIG. 20, when the signal RESET isinputted to the logic unit 7 shown in FIG. 19, the logic unit 7 executesvarious logic operations and outputs the signal RST, so that the resetoperation of the word line is started. At the same time, the control isoutputted from the node sw00 of the logic unit 7 and starts monitoringthe potential of the word line. In this case, the potential, the voltageof which is divided by the resistance ratio of the four voltage-dividingresistors 74 to 77, can be obtained at the node sw01.

The potential at the node sw02 can be obtained depending on theresistance ratio between the ON resistance of the P-channel transistor91, which is controlled by the level of the node sw01, and theresistance (r10) of the resistor 92, and the potential of this node sw02operates the inverter of the next stage.

Here, when the potential of the word line is high, the node sw01 existsat the level which is recognized as “H”. In consequence, the node sw02is “L” and the switch signal SW is “L”, too. Next, when the potential ofthe word line drops sufficiently, the potential of the node sw01 dropsto a level which is recognized as “L”, and brings the P-channeltransistor 91 of the next stage into the operative state. At this time,the ON resistance of the P-channel transistor 91 is sufficiently smallerthan the resistance value r10 of the resistor 92 and the node sw02 is“H”. As a result, the switch signal SW changes to “H”. The switch signalSW, which changes from “L” to “H” in this way, is supplied as the resetpotential switch control signal to the node n02 shown in FIG. 6 or 8.

First, according to the semiconductor devices of the first to thirdembodiments of the present invention as explained above, the reset levelfor executing the reset operation of the word line connected to thememory cell is switched between the first potential, such as the groundpotential, and the second potential, such as the negative potential. Inconsequence, the major proportion of the charges held by the node of theword line are allowed to escape to the power source of the groundpotential, the amount of the charges allowed to be escape to the powersource of the negative potential, which has low power source efficiency,can be drastically reduced, and power consumption can be reduceddrastically.

Next, the semiconductor devices of the first to third embodiments of thepresent invention include the reset level switch circuit unit forswitching the first and second potentials of the reset level inside theword line drive circuit. Therefore, the major proportion of the chargesheld by the node of the word line can be extracted directly to the powersource of the ground potential, and the reset operation can be carriedout stably without being affected by the threshold voltages of thetransistors.

In the semiconductor devices of the first to third embodiments of thepresent invention, the reset level switch circuit for switching thefirst and second potentials of the reset level is disposed separatelyfrom the word line drive circuit. Therefore, the unoccupied space on thesemiconductor chip can be utilized effectively, and the area of thesemiconductor chip can be limited to a minimum.

In the fourth place, in the semiconductor devices according to the firstto third embodiments, a plurality of word drive circuits share the resetlevel switch circuit and the switching operation of the first and secondpotentials of the reset level is collectively executed. Therefore,unnecessary consumption of power by the reset level switch circuit canbe restricted.

In the fifth place, in the semiconductor devices according to the firstto third embodiments of the present invention, the switching operationto the ground potential of the reset level is executed before the startof the reset operation of the word line and in this way, the majorproportion of the charges held by the node of the word line are allowedto escape to the power source of the ground potential. Consequently,power consumption can be drastically saved.

In the sixth place, in the semiconductor devices according to the firstto third embodiments of the present invention, the switching operationof the reset level to the negative potential is executed after the levelof the word line has dropped sufficiently. Therefore, the amount of thecharges caused to escape to the negative power source having low powersource efficiency can be drastically decreased and power consumption canbe saved drastically.

In the seventh place, according to the first to third embodiments of thepresent invention, the switching operation of the reset level betweenthe first and second potentials can be executed by using the activationsignal and the non-activation signal of the sense amplifier provided tothe memory cell array. Therefore, the control signal need not be appliedfor switching the reset level, and the increase in power consumptionresulting from an excessive circuit operation by this control signal,can be restricted.

Next, some preferred embodiments for accomplishing the second object ofthe present invention will be explained.

When the semiconductor device comprises a plurality of banks, the wordline reset level generating circuit comprises a plurality of circuitunits, that correspond to a plurality of banks and can operateindependently, and these circuit units are selected in accordance withthe operation of the memory cell array.

It is practically preferred to supervise the output state of the wordline reset level generating circuit and to execute the feed-backcontrol. FIG. 21 is a block diagram showing the construction of thebasic embodiment based on the principle for accomplishing the secondobject of this invention. As shown in this drawing, a WL (word line)reset level generating circuit 400 is disposed in addition to the memorycell array 100, the word line driver 200 and the row decoder 300.Furthermore, the semiconductor device of this embodiment is providedwith a reset level detecting circuit 500 for detecting the output stateof the word line reset level generating circuit and a reset levelcontrol Circuit 600 for controlling the operation of the word line resetlevel generating circuit on the basis of the detection result of thereset level detecting circuit. In this case, the reset level controlcircuit is allowed to operate in such a manner that the operation of theword line reset level generating circuit stops when its output is belowa first predetermined voltage, the amount of the current supply of theword line reset level generating circuit becomes maximal when its outputexceeds a second predetermined voltage, and the amount of the currentsupply of the word line reset level generating circuit is controlled inaccordance with the access operation to the memory cell array when itsoutput is in between the first and second predetermined voltages.

When the word line reset level generating circuit includes anoscillation circuit, a capacitor and a capacitor drive circuit fordriving the capacitor, the high potential side power source potential ofthe capacitor drive circuit is set to a potential higher than, or equalto, or lower than, the higher potential of the power source of theoscillation circuit in accordance with stability of the external powersource, its voltage condition, and so forth. The oscillation signaloutputted from the oscillation circuit and applied to the capacitorthrough the capacitor drive circuit is a single signal, or a pluralityof signals in some cases.

When the word line reset level generating circuit includes anoscillation circuit, a capacitor and a capacitor drive circuit fordriving the capacitor, the semiconductor device is provided with a powersource switch circuit for switching the connection of the power sourceline of higher potential of the capacitor among a plurality of powersource lines having different potentials, and changes the supply amountof the word line reset level generating circuit. In this case, the powersource switching circuit is switched between the power source linehaving a potential higher than the higher potential of the power sourceof the oscillation circuit and the power source line having a potentialequal to the higher potential of the power source, or between the powersource line having a potential equal to the higher potential of thepower source of the oscillation circuit and the power source having alower potential.

Another method of changing the amount of the current supply of the wordline reset level generating circuit comprises the steps of disposing aplurality of oscillation circuits for outputting oscillation signalshaving different frequencies and a selection circuit for selecting theoscillation signal from a plurality of oscillation circuits to besupplied to the capacitor drive circuit, and changing the frequency ofthe capacitor drive signal.

Still another method of changing the amount of the current supply of theword line reset level generating circuit comprises the steps ofconstituting the capacitor and the capacitor drive circuit into aplurality of units, disposing a switch for switching the input to eachcapacitor drive circuit unit and switching the switch in accordance withthe operation of the memory cell array.

The methods described above can be used in combination as the method ofchanging the amount of the current supply of the word line reset levelgenerating circuit.

The operation becomes stable if an internal regulator circuit fordown-converting the power source voltage supplied from outside is usedas the power source for the oscillation circuit.

FIG. 22 is a block diagram showing the bank construction of the DRAMchip 700 of the fourth embodiment of the present invention and thedisposition of the WL reset level generating circuit inside the chip700. As shown in the drawing, the memory cell is divided into 16 blocks.Inside each block are disposed the word line, the bit line, the memorycell, the sense amplifier, the word decoder, the word driver, the columndecoder, the data amplifier, the write amplifier, etc., in the same wayas in the ordinary DRAM. These sixteen blocks are grouped into fourbanks, and the blocks of the same bank are accessed in parallel. In thisexample, therefore, four blocks are accessed in parallel with oneanother. Since eight memory cells are accessed in parallel in eachblock, the data width is a 32-bit width.

The WL reset level generating circuit, too, comprises four circuit units400-0 to 400-3 corresponding to the number of banks, and these circuitunits are disposed at the center of the chip 700. The negativepotentials generated by the circuit units 400-0 to 400-3 are supplied toeach block through a wiring 900. Incidentally, the arrangementillustrated hereby is an example, and various modifications can be made.Furthermore, the number of banks and their arrangement, too, can bemodified, and various arrangements can be employed. Incidentally, thereset level detecting circuit and the reset level control circuit arenot shown in FIG. 22 but they are disposed in the proximity of thecircuit units 400-0 to 400-3 of the WL reset level generating circuit.

FIG. 23 is a block diagram showing the functional construction of theDRAM according to the fourth embodiment. As shown in the drawing, theaddress signal inputted from an address port 110 is supplied to the rowdecoder 300 and the column decoder 140 of each bank. The row selectionsignal outputted from the row decoder 300 is applied to each word line150 through the word line driver 200, and activates the word line(selected word line) connected to the memory cell to which access ismade. Other word lines (non-selected word lines) are kept under thenon-activated state. The column selection signal outputted from thecolumn decoder 140 is applied to the sense amplifier series 172 andactivates the sense amplifier connected to the bit line to which thememory cell to be accessed is connected. Other sense amplifiers are keptunder the non-activated state. The address signal and the control signal(not shown in the drawing) that are inputted are supplied to the logiccircuit 120, and the internal control signals generated in this logiccircuit 120 are supplied to each bank. In the data write operation, thewrite data inputted to the I/O port 130 is supplied to the senseamplifier series 172 through the write amplifier 190, and the senseamplifier so activated sets the bit line to the state corresponding tothe write data. The memory cell connected to the selected word lineenters the state corresponding to the state of this bit line. In thedata read-out operation, the state of the bit line changes in accordancewith the state of the memory cell connected to the selected word line,and this state is amplified by the sense amplifier that is activated.The data amplifier 180 outputs this state to the I/O port 130. Theexplanation given above explains the general construction according tothe prior art.

The DRAM according to the fourth embodiment includes the WL (word line)reset level generating circuit 400, the reset level detecting circuit500 and the reset level control circuit 600, as shown in the drawing.The WL reset level generating circuit 400 supplies the negativepotential output to the word line driver 200 and the row decoder 300 ofeach block. The reset level detecting circuit 500 detects the level ofthe negative potential output of the WL reset level generating circuit400 and outputs the detection result to the reset level control circuit600. The reset level control circuit 600 controls the negative potentialgenerating operation of the WL reset level generating circuit 400 on thebasis of the detection result.

FIG. 24 is a block diagram showing in further detail the constructionsof the WL reset level generating circuit 400, the reset level detectingcircuit 500 and the reset level control circuit 600 of the fourthembodiment. As shown in the drawing, the WL reset level generatingcircuit 400 comprises n WL reset level generating circuit units(hereinafter referred to as the “generating circuit units”) 400-0 to400-n, and the reset level control circuit 600 comprises n reset levelcontrol circuit units (hereinafter referred to as the “control circuitunits”) 600-0 to 600-n, too. In the fourth embodiment, n represents thebank number and is, for example, 4. The control circuit units 600-0 to600-n and the generating circuit units 400-0 to 400-n constitute pairs,respectively, and each control circuit unit 600-0 to 600-n generates thecontrol signal EN0 to ENn that changes over the corresponding generatingcircuit unit 400-0 to 400-n between the operating state and thenon-operating state. The outputs of the generating circuit units 400-0to 400-n are connected in common, and are outputted as the negativepotential output vnwl. The reset level detecting circuit 500 comprisesthe first reset level detecting circuit 500-1, that detects whether ornot the negative potential output vnwl is below the first referencelevel V4 and outputs the V4 detection signal, and the second reset leveldetecting circuit 500-2 that detects whether or not the negativepotential output vnwl is above the second reference level V5 and outputsthe V5 detection signal. The detection results of the first and secondreset level detecting circuits 500-1 and 500-2 are inputted to eachcontrol circuit unit 600-0 to 600-n. Each control circuit unit 600-0 to600-n generates the control signal EN0 to ENn on the basis of the V4 andV5 detection signals and the bank selection signal BA.

FIG. 25 is a block circuit diagram showing the construction of eachgenerating circuit unit 400-0 to 400-n. As shown in this drawing, eachgenerating circuit unit includes the oscillation circuit 210, the levelconverting circuit 220, the capacitor drive circuit 230, the capacitor240 and the output circuit (transistor) 250. The operation of theoscillation circuit 210 is controlled by the control signal EN from eachcontrol circuit unit 600-0 to 600-n. A voltage corresponding to thehigher potential of the power source of the oscillation circuit 210 isV2 and a voltage corresponding to the higher potential of the powersource of the capacitor drive circuit 230 is V3. The voltages of thesetwo circuits are mutually different. For this reason, the levelconverting circuit 220 is disposed. The power source (V3) of thecapacitor drive circuit 230 is the power source supplied from outside,for example, and the power source (V2) of the oscillation circuit 210 isthe power source obtained by regulated voltage power source in the chip.

FIGS. 26A and 26B show structural examples of the internal regulatorcircuit, wherein Vdd represents the external power supply and V2 doesthe internally regulated voltage. Therefore, Vdd corresponds to V3 inthe fourth embodiment. The circuit shown in FIG. 26A uses a negativefeedback circuit that uses in turn a driver of a P-channel transistor,and outputs a potential equal to vref as V2. Therefore, if an accuratepotential generated by a constant potential power source is used asvref, a stable internally regulated power source (V2) can be obtainedeven when the external power supply Vdd fluctuates. FIG. 26B′shows aregulator circuit using an N-channel transistor. When the gate voltageof the N-channel transistor is Vg, V2 is Vg−Vth (threshold voltage ofthe transistor). Similarly, if an accurate potential generated by theconstant potential is used as Vg, a stable internally regulated voltageV2 can be obtained even when the external power supply Vdd fluctuates.If the internally regulated voltage V2 is stable, the cycle of theoscillation signal generated by the oscillation circuit 210 can bestabilized. Since the voltage V3 is higher than the internally regulatedvoltage V2, the current supply capacity of the vnwl generating circuitcan be increased and the increase of the chip area can be suppressed.Incidentally, the on-chip regulator can be used as V3, too, andfurthermore, V2 can be made equal to V3. In this case, the levelconverting circuit 220 can be omitted.

FIG. 27 is a circuit diagram showing a concrete circuit construction ofthe WL reset level generating circuit unit of the fourth embodiment.Because the construction of each of the oscillation circuit 210, thelevel converting circuit 220, the capacitor drive circuit 230, thecapacitor 249 and the output circuit is well known, a detaileddescription will be omitted. The control signal EN is inputted to theNAND gate of the second stage of the oscillation circuit 210 so that theoperation of the oscillation circuit can be controlled. Incidentally,the control signal vtx inputted to the NAND gate of the fifth stage ofthe oscillation circuit and to the output portion is the externalcontrol signal, and is used for compulsively stopping the WL reset levelgenerating circuit irrespective of the EN signal. As shown in thedrawing, the power source of the oscillation circuit 210 is V2, and thepower source of the capacitor drive circuit 230 is V3 which is higherthan V2.

Therefore, the oscillation signal of the oscillation circuit 210 isconverted by the level converting circuit 220 to the level correspondingto V3 and is then applied to the capacitor drive circuit 230.

FIG. 28 is a circuit diagram showing the circuit construction of amodified example of the WL reset level generating circuit unit. Thecircuit shown in FIG. 28 uses in common the internally regulated powersource (V2) for both the oscillation circuit 210 and the capacitor drivecircuit 230. The level converting circuit 220 is deleted because it isnot necessary. The rest of the constructions are the same as those shownin FIG. 27.

FIG. 29 is a circuit diagram showing the circuit construction of anothermodified example of the WL reset level generating circuit unit. Thecircuit shown in FIG. 29 uses a power source (V6) lower than the powersource (V2) of the oscillation circuit 210 as the power source of thecapacitor drive circuit 230. Since V6 is lower than V2, the capacitordrive circuit 230 can be driven by the output of the oscillation circuit210 without using the level converting circuit 220. The rest of theconstructions are the same as those shown in FIG. 27.

FIGS. 30A to 30D show the circuit constructions of the WL reset leveldetecting circuit. Any of the circuits shown in FIGS. 30A to 30D candetect whether the negative potential output vnwl is higher, or lower,than a predetermined level. Since this predetermined level varies withthe size of the transistors that constitute the circuit, the circuit canbe constituted into the first reset level detecting circuit 500-1 fordetecting whether or not the negative potential output vnwl is below thefirst reference level V4, or into the second reset level detectingcircuit 500-2 for detecting whether or not the negative potential vnwlis higher than the second reference level V5. Incidentally, the controlsignal vtx for compulsively stopping the circuit from outside isinputted to this circuit, too.

FIG. 31 is a circuit diagram showing the circuit construction of thereset level control circuit units 600-0 to 600-n, and FIG. 32 is atiming chart useful for explaining the control operation of the WL resetlevel control circuit unit. As shown in a portion (1) of FIG. 32, thelevel of the negative potential is sufficient when the negativepotential vnwl is lower than V4. Since the voltage need not be generatedany more, the operations of all the generating circuit units 400-0 to400-n are stopped. Since the level of the negative potential isinsufficient when the negative potential vnwl is higher than V5, all thegenerating circuit units 400-0 to 400-n are operated. Since the level ofthe negative potential vnwl is neither insufficient nor sufficient whenthe negative potential vnwl is higher than V4 and lower than V5, thegenerating circuit unit corresponding to the bank, to which access ismade, is operated in accordance with the access operation of the memorycell array, or more concretely, in accordance with the access operationof the bank. As shown in a portion (2) of FIG. 32, both V4 and V5 are“L” when the negative potential vnwl is lower than V4, EN is “L”irrespective of the bank selection signal BA, and the oscillation signalOS is not outputted from the oscillation circuit 210. When the negativepotential output vnwl is higher than V4 and lower than V5, V4 is “H”while V5 is “L”. When the bank selection signal BA is “H”, EN is “H”.When BA is “L”, EN is “L”, and the oscillation signal OS is outputtedfrom the oscillation circuit 210 in accordance with BA. When thenegative potential vnwl is higher than V5, both V4 and V5 are “H”, EN is“H” irrespective of the bank selection signal BA, and the oscillationsignal OS is outputted from the oscillation circuit 210.

As described above, in the fourth embodiment, the reset level generatingcircuit 400 is constituted by a plurality of units, and the amount ofthe current supply of the negative potential of the word line resetlevel generating circuit 4 is varied depending on how many units areoperated. All the units are caused to stop in accordance with the levelof vnwl or a part of them is operated in accordance with the accessoperation of the memory cell array. Therefore, the unnecessary operationof generating the negative potential is inhibited while the necessarynegative potential is maintained, and power consumption can be reduced.

The negative potential vnwl generated in the manner described above issupplied to the word line driver 200 and to the row decoder 300. FIG. 33is a circuit diagram showing the circuit construction of the word linedriver 200 and the row decoder 300 in the fourth embodiment. Thiscircuit employs a hierarchical word line scheme for selecting one of aplurality of swl for one mwl. In the row decoder 300, one main word linemwl is selected by the row address signals addaz and addbz and by theblock selection signal BLS. In the word line driver 200, on the otherhand, one sub-word line swl is selected by the signal swdz for oneselected main word line mwl, and the word line WL to be activated isdecided. The negative potential vnwl is used for the lower potential ofthe power source of the word line driver 200 and the row decoder 300. Inthis case, mwl and swl have mutually opposite polarities, and both havenegative potential vnwl on the lower potential.

FIGS. 34 to 36 are timing charts showing the operation of the DRAM ofthe fourth embodiment. FIG. 34 shows the case where access is made toonly one bank 0, FIG. 35 shows the case in which access is made to twobanks, for example, the banks 0 and 2, and FIG. 36 shows the case inwhich access is made to four banks 0 to 3. As shown in these drawings,the potential of the accessed bit line on the lower potential is zeroand the potential of the non-selected word lines is a negative potentiallower than zero. In the timing charts, since the signal relating to thenegative potential output vnwl shifts at the timings represented byellipses, the current which merely charges and discharges the load ofthe word line (here, the main-word lines and sub-word lines) flowsthrough the power source line of the negative potential vnwl. Therefore,the WL reset level generating circuit 400 must have a capacitysufficient to absorb only this current. However, only the minimum timeis set to the bank activation period but the maximum time is notstipulated. Therefore, the difference occurs in the necessary current,and also occurs between the case in which only one bank is activated soas to actiVate the word line and the case in which four banks areactivated to activate the word lines in parallel. Since a large currentdifference exists, depending on the internal operating condition, it iseffective to employ the scheme in which the generating circuit unit isdisposed for each bank and the operation is controlled in accordancewith the bank selection signal BA as in this embodiment.

Incidentally, in the control system shown in FIG. 32, the controloperation can be executed by disposing only one of the first and secondword line reset level detecting circuits and by setting only one of V4and V5. Such a control may be executed for only a part of a plurality ofsets of generating circuit units and control circuit units. In otherwords, a part of the control circuit units 600-0 to 600-n is omitted andthe bank selection signal BA is directly inputted to the generatingcircuit unit for the omitted portion or the generating circuit unit isalways kept under the operating condition.

If the access operation to any of the banks is always executed and theamount of the current supply of the negative potential vnwl, that ispractically necessary, is proportional to the number of banks accessedin the control operation described above, the first and second resetlevel detecting circuits 500-1 and 500-2 and the control units 600-0 to600-n shown in FIG. 24 need not be disposed, and the bank selectionsignals BA0 to Ban are directly inputted to the generating circuit units400-0 to 400-n in place of the control signals EN0 to ENn.

FIG. 37 is a block circuit diagram showing the construction of amodified example of the WL reset level generating circuit in the fourthembodiment. In the construction shown in FIG. 25, this modified exampledivides the level converting circuit 220 into a plurality of levelconverting circuit units 220-0 to 220-n, the capacitor drive circuit 230into a plurality of capacitor drive circuit units 230-0 to 230-n, thecapacitor 240 into a plurality of capacitor units 240-0 to 240-n and theoutput circuit 250 into a plurality of output circuit units 250-0 to250-n, respectively, and combines the divided circuit units into n sets.The oscillation signals OS0 to OSn having different phases are suppliedfrom the common oscillation circuit 210 to each set. The output of eachset is connected in common. This modified example is effective when thepumping capacity 240 is large with respect to the cycle of theoscillation signal. When the cycle of the oscillation signal becomesshort, a large capacitor cannot be charged sufficiently and currentsupply efficiency drops. In consequence, the cycle of the oscillationsignal cannot be much reduced. It is preferred, on the other hand, toshorten the cycle of the oscillation signal in order to restrict theincrease of the area of the negative potential generating circuit and torestrict the increase of its current consumption. If the output of eachset is connected in common and the oscillation signal having a differentphase is inputted to each set as in this modified example, currentsupply efficiency does not deteriorate even when the cycle of theoscillation signal becomes so short as only a small capacitor has to becharged in a short period, since the current is supplied with other setsalternately.

FIG. 38 is a circuit diagram showing the circuit construction of the WLreset level generating circuit unit embodying the modified exampledescribed above, and shows the example of division into two sets. Asshown in the drawing, this circuit includes the oscillation circuit 210,two level converting circuits 220A and 220B, two capacitor drivecircuits 230A and 230B, two capacitors 240A and 240B, and two outputcircuits. In other words, the circuit of FIG. 38 corresponds to the casewhere two generating circuit units shown in FIG. 27 are disposed, theoscillation circuit 210 is used in common, and two oscillation signalshaving different phases from the oscillation circuit 210 are inputted tothe capacitor drive circuits 230A and 2303, According to this circuitconstruction, two capacitors 240A and 240B are driven by two oscillationsignals having substantially opposite phases, and because the outputs oftwo sets of generating circuit units are connected in common, ripples ofthe outputs corresponding to the capacitor dumping can be reduced muchmore than in the construction shown in FIG. 27. Incidentally, it is alsopossible to drive the capacitor by three or more different oscillationsignals by disposing three or more sets of the level converting circuit,the capacitor drive circuit, the capacitor and the output circuit.

The construction in which a plurality of sets of the capacitor drivecircuit, the capacitor and the output circuits are disposed and theoscillation circuit is used in common as shown in FIG. 38 can be appliedto any of the circuits shown in FIGS. 27, 28 and 29.

FIG. 39 is a block circuit diagram showing the construction of each ofthe WL reset level generating circuit 400, the reset level detectingcircuit 500 and the reset level control circuit 600 according to thefifth embodiment. The construction of this fifth embodiment is differentfrom that of the fourth embodiment in that the reset level detectingcircuit 500 is not divided. The reset level detecting circuit 500detects whether the negative potential vnwl is lower than V4 or higherthan V5. The reset level detecting circuit 500 of the fifth embodimentcollectively executes, in a sense, the functions of the first and secondreset level detecting circuits 500-1 and 500-2 of the fourth embodiment.The rest of portions are the same as those of the fourth embodiment.

FIGS. 40A, 40B, 41A and 41B are circuit diagrams showing the structuralexamples of the reset level detecting circuit 500 in the fifthembodiment. These circuits, too, can adjust the levels of V4 and V5 byadjusting the sizes of the transistors, and the explanation in furtherdetail will be omitted.

In the fourth and fifth embodiments, the reset level generating circuit400 comprises a plurality of units, and the amount of the current supplyof the negative potential of the reset level generating circuit 400 isvariable depending on how many units are operated. Various other methodsare available to vary the amount of the current supply of the negativepotential of the reset level generating circuit 400, such as a methodthat changes the power source potential of the capacitor drive circuit,a method that changes the cycle of the oscillation signal for drivingthe capacitor, a method that changes the size of the capacitor, and soforth. These methods can be applied to the whole, or a part, of aplurality of reset level generating circuit units of the fourth andfifth embodiments. Hereinafter, some embodiments applying these methodswill be explained.

FIG. 42 is a circuit diagram showing the basic construction of the WLreset level generating circuit of the sixth embodiment. This embodimentrepresents the example in which the negative potential current supply ismade variable by applying a method, that changes the power sourcepotential of the capacitor drive circuit, to the WL reset levelgenerating circuit having a similar construction to the constructionshown in FIG. 37. As shown in the diagram, each capacitor drive circuit230-0 to 230-n is connected to two power sources having differentpotentials through the transistor operating as a switch. Here, it isconnected to the external power supply V3 and to the internal powersource V2 obtained by down-converting the above external power supplyV3. The switch signal VSW is applied to the transistor operating as theswitch, and any of the transistors becomes conductive. Since the powersupply V3 is higher than V2, when the capacitor drive circuit isconnected to V3, the amplitude of the capacitor drive signal is largerthan in the case of capacitor drive circuit being connected to V2.Therefore, the current supply of the WL reset level generating circuitbecomes increased without increasing the area.

FIGS. 43A and 43B are a circuit diagram and a timing chart showing theconcrete circuit construction of the WL reset level generating circuitof the sixth embodiment and its operation. As shown in FIG. 43A, thisembodiment disposes a circuit 260 for switching the power source of thecapacitor drive circuit 230 in the circuit of the fourth embodimentshown in FIG. 27. As shown in FIG. 43B, the negative potential isgenerated when the control signal EN is “H” and the oscillation signaln00 is generated. Since the power source V3 is connected when the switchsignal VSW is “L”, the mean supply current (or average supply current)of this WL reset level generating circuit is great, but when the switchsignal VSW is “H”, the power source V2 is connected. Therefore, the meansupply current of this WL reset level generating circuit becomes small.

Incidentally, the method that switches the power source of the capacitordrive circuit 230 of the sixth embodiment can be applied also to thecircuits shown in FIGS. 28 and 29.

FIG. 44 is a block circuit diagram showing the basic construction of theWL reset level generating circuit of the seventh embodiment. Thisembodiment represents the example in which the method of changing thecycle of the oscillation signal for driving the capacitor is applied tothe WL reset level generating circuit having a similar construction tothe construction shown in FIG. 37 so as to make the current supply ofthe negative potential variable. As shown in the drawing, a high-speedoscillation circuit 210A for outputting a high-frequency oscillationsignal and a low-speed oscillation circuit 210B for outputting alow-frequency oscillation signal are disposed in place of theoscillation circuit 210, and the output of which circuit is inputted toeach level converting circuit 220-0 to 220-n is selected by the transfergate circuit 270. The transfer gate is controlled by the switch controlsignal. As described above, the shorter becomes the cycle of theoscillation signal that drives the capacitor, the larger becomes themean supply current. Therefore, when the high-frequency oscillationsignal is inputted to each level converting circuit 220-0 to 220-n, themean supply current becomes large.

FIG. 45 is a circuit diagram showing the concrete circuit constructionof the WL reset level generating circuit of the sixth embodiment andFIG. 46 is a timing chart showing the operation of this circuit. Asshown in FIG. 45, this embodiment disposes a high-speed oscillationcircuit 210A and a low-speed oscillation circuit 210B in place of theoscillation circuit 210 in the circuit of the fourth embodiment shown inFIG. 27. The control signal EN, too, comprises a control signal ENA forcontrolling the operation of the high-speed oscillation circuit 210A anda control signal ENB for controlling the operation of the low-speedoscillation circuit 210B, and these control signals ENA and ENB are usedalso as the switch control signal. As shown in FIG. 46, the high-speedoscillation circuit 210A generates a high-frequency oscillation signaln00 when the control signal ENA is “H” and the control signal ENB is“L”, and this signal n00 is inputted to the level converting circuit220. Since the low-speed oscillation circuit 210B does not operate atthis time, the low-frequency oscillation signal n01 is not generated.Because the capacitor is driven by the high-frequency oscillation signaln00, the mean supply current of the WL reset level generating circuit islarge. The low-speed oscillation circuit 210B generates a low-frequencyoscillation signal n01 when the control signal ENA is “L” and ENB is“H”, and this signal is inputted to the level converting circuit 220.Since the high-speed oscillation circuit 210A does not operate at thistime, the high-frequency oscillation signal n00 is not generated.Because the capacitor is driven by the low-frequency oscillation signaln01, the mean supply current of the WL reset level generating circuit issmall, and the consumed current becomes small.

Incidentally, the method of changing the cycle of the oscillation signalfor driving the capacitor according to the seventh embodiment can beapplied also to the circuits shown in FIGS. 28 and 29.

FIG. 47 is a circuit diagram showing the basic construction of the WLreset level generating circuit according to the eighth embodiment. Thisembodiment represents the example that makes the power source potentialof the capacitor drive circuit in the sixth embodiment variable bycombining the method that changes the power source potential of thecapacitor drive circuit in the sixth embodiment, with the method thatchanges the cycle of the oscillation signal for driving the capacitor inthe seventh embodiment. FIG. 48 is a circuit diagram showing theconcrete circuit construction of the eighth embodiment, and FIG. 49 is atiming chart showing its operation. The explanation in detail will beomitted. The method of the eighth embodiment can be applied also to thecircuits shown in FIGS. 28 and 29.

FIG. 50 is a circuit diagram showing the basic construction of the WLreset level generating circuit according to the ninth embodiment. Thisembodiment represents the example in which the amount of the currentsupply of the negative potential is made variable by applying themethod, that changes the size of the capacitor, in the WL reset levelgenerating circuit shown in FIG. 37. As shown in the drawing, there isdisposed a switch circuit 280 for inhibiting the input of theoscillation signal to a part of the level converting circuit so as toinhibit the operation of the set of a part of the units. According tothis circuit construction, the size of the capacitor used substantiallychanges, and the mean supply current changes. The switch circuit 280 iscontrolled by a capacitor area control signal ACS. Incidentally, if thesame oscillation signal is used, it is possible to use in common thelevel converting circuit and to dispose the switch circuit at the inputportion of each capacitor drive circuit.

FIG. 51 is a circuit diagram showing the concrete circuit constructionof the WL reset level generating circuit of the ninth embodiment, andFIG. 52 is a timing chart showing its operation. As shown in FIG. 51, inthe circuit of the modified example of the fourth embodiment shown inFIG. 38, this embodiment can inhibit the input of the oscillation signaln01 to the level converting circuit 220A of one of the sets inaccordance with ACS and can also inhibit the input of the oscillationsignal n00 to the power source drive portion of the capacitor 240A. Theoscillation signal n00 is always inputted to the level convertingcircuit 220B of the other set, and the oscillation signal n01 is alsoinputted always to the power source driving portion. Therefore, theother set always operates.

As shown in FIG. 52, this WL reset level generating circuit operateswhen the control signal EN is “H”, and both of two sets operate when ACSis “H”. Consequently, the mean supply current becomes large. When ACS is“L”, on the other hand, one of the sets does not operate, and the meansupply current becomes small.

FIGS. 53A and 53B are circuit diagram and a timing chart showing thecircuit construction of the WL reset level generating circuit of amodified example of the ninth embodiment and its operation. In thisexample, two sets of the driving circuits 230A and 230B and thecapacitors 240A and 240B are disposed as shown in FIG. 53A, and theinput of the oscillation signal after level conversion to one of thecapacitor drive circuits (230B) can be inhibited in accordance with ACS.Since the operation is analogous to that of FIG. 52, as shown in FIG.53B, the explanation in further detail will be omitted.

Though the fourth to ninth embodiments of the present invention havethus been explained, the constructions of these embodiments can becombined in various ways as already explained, and it is of importanceto use an optimum method in accordance with the intended application.

As explained above, in the semiconductor device that extends the dataholding time by reducing the sub-threshold leakage current by settingthe reset level of the word line to the negative potential, the fourthto ninth embodiments of the present invention can accomplish theimprovements in the characteristics such as low power consumption, thestable operation, etc., and they are particularly effective for thosesemiconductor devices for which scaling-down of the size and highintegration density have been attempted.

Next, some preferred embodiments for accomplishing the aforementionedthird object of the present invention will be explained.

Though the invention dealt with by these embodiments can be applied tovarious semiconductor devices, the following embodiments will illustratethe examples in which the embodiments are applied to dynamic randomaccess memories (DRAMs).

FIG. 54 is a schematic view showing the bank construction of the DRAMchip 700 according to the tenth embodiment of the present invention. Asshown in the drawing, the memory cell array is divided into sixteenblocks. Each block includes the word line, the bit line, the memorycell, the sense amplifier, the word decoder, the word driver, the columndecoder, the data amplifier, the write amplifier, etc., in the same wayas the ordinary DRAM. These sixteen blocks are divided into four banks,and the blocks of the same bank are accessed in parallel. In thisembodiment, therefore, four blocks are accessed in parallel. In thiscase, for example, since eight memory cells are accessed in parallel ineach block, the data width is a 32-bit data width.

FIG. 55 is a block diagram showing the functional construction of theDRAM according to the tenth embodiment. As shown in the drawing, theaddress signal inputted from the address port 110 is supplied to the rowdecoder 300 and the column decoder 140 of each bank. The row selectionsignal outputted by the row decoder 300 is applied to each word line 150through the word line driver 200 and activates the word line connectedto the memory cell to which access is made (selected word line), andother word lines (non-selected word lines) are kept in the non-activatedstate. The column selection signal outputted by the column decoder 140is applied to the sense amplifier series 172 and activates the senseamplifier connected to the bit line to which the memory cell, that is tobe accessed, is connected. Other sense amplifiers are kept in thenon-activated state. The address signal and the external control signal(not shown in the drawing) inputted are supplied to the logic circuit120, and the internal control signal generated in this circuit issupplied to each bank. When the data is written, the write data inputtedto the I/O port 130 is supplied to the sense amplifier series 172through the write amplifier 190, and the sense amplifier so activatedsets the bit line to the state corresponding to the write data. Thepotential state (charges) corresponding to the state of this bit line isstored in the memory cell connected to the selected word line. When thedata is read out, the state of the bit line changes in accordance withthe stored charges of the memory cell connected to the selected wordline, and the sense amplifier that is activated amplifies this data. Thedata amplifier 180 outputs this data to the I/O port 130. Thisexplanation deals with the ordinary construction of the prior art. Inaddition to such a construction, the DRAM according to the tenthembodiment includes a power source circuit 410 for generating apotential different from the external power supply, as shown in FIG. 4.

The DRAMs of the recent type include the on-chip power source circuit orinternal power source circuit for generating the power source having apotential other than the external input power supply Vdd and GND asshown in FIG. 4. FIG. 4 shows the step-up potential Vppr used forgenerating Vg and Vpp for the “H” level of the selected word line, theword line reset level Vnwl, and back-bias Vbb. These potentials aregenerated by the power source circuit that drives the capacitor by theoscillation signal. The power source circuit shown in FIG. 55illustrates such a power source circuit as a whole.

FIG. 56 is a block circuit diagram showing the basic construction of thepower source circuit 400 according to the tenth embodiment. As shown inthe drawing, the power source circuit 400 includes the capacitor drivecircuits 230-01 to 230-0 n and 230-11 to 230-1 m, the capacitors(pumping capacitors) 240-01 to 240-0 n and 240-11 to 240-1 m and theoutput circuit having the output transistors 250-01 to 250-0 n and250-11 to 250-1 m. The capacitor drive circuit, the capacitor and theoutput circuit form a pair and constitute the power source circuit unit.Incidentally, the output circuit in FIG. 56 comprises the transistor.The oscillation signal is supplied from the common oscillation circuit210 to each capacitor drive circuit 230-01 to 230-0 n and 230-11 to230-1 m. The oscillation signal supplied to each capacitor drive circuitmay be the same signal, or signals having different cycles, or signalshaving the same cycle but different phases. Each power source circuitunit generates the potentials Vp01 to Vp0 n and Vp11 to Vp1 m. Eachpower source circuit that comprises the capacitor drive circuit 230-01to 230-0 n, the capacitor 240-01 to 240-0n and the output transistor250-01 to 250-0 n represents the negative voltage generating circuit,and each power source circuit that comprises the capacitor drive circuit230-11 to 230-1 m, the capacitor 240-11 to 240-1 m and the outputtransistor 250-11 to 250-1 m represents a boosting circuit forgenerating a step-up voltage. The oscillation circuit 210 can stops itsoscillation by the control signal EN. When the oscillation circuit 210stops its oscillation, no oscillation signal is outputted. Therefore,each power source circuit stops its operation, too. In other words, theoperation of the power source can be controlled by the control signalEN.

As shown in the drawing, the internally regulated power source (V2) ofthe oscillation circuit 210 and the internally regulated power sources(V31 to V3 n and V311 to V31 m) of each capacitor drive circuit 230-1 to230-0 n and 230-11 to 230-1 m are different (this difference may be onlya partial difference). Here, the external power source Vdd is used asthe power sources V31 to V3 n and V311 to V31 m, while V2 is generatedfrom the external power supply vdd by using the internal regulatorcircuit shown in FIGS. 57A and 57B. FIG. 57A shows the circuit using thenegative feedback circuit using the driver of the P-channel transistor,and this circuit outputs a potential equal to vref as V2. Therefore, ifthe correct and constant voltage is used as vref, the stable internallyregulated power source (V2) can be obtained even when the external powersupply Vdd changes. FIG. 57B shows a regulator circuit using theN-channel transistor. When the gate voltage of the N-channel transistoris Vg, V2 is given by Vg−Vth (Vth: threshold value of the transistor).Similarly, if the correct and constant voltage is used as Vg, the stableinternally regulated power source V2 can be obtained even when theexternal power supply Vdd fluctuates. If V2 is stable, the cycle of theoscillation signal generated by the oscillation circuit 210 can bestabilized. Since V3 is higher than V2, the current supply capacity canbe increased and the increase of the chip area can be suppressed.Incidentally, it is possible to use the internally regulated powersource as V2 or to make V2 equal to V3. Furthermore, both of V2 and V3can be the external power supply Vdd. In this case, however, the cycleof the oscillation signal of the oscillation circuit is affected by thevalue of the external power supply.

FIGS. 58 and 59 are circuit diagrams showing the concrete circuitconstruction of the power source circuit according to the tenthembodiment, and represent the case in which two negative voltagegenerating circuits (that is, n=2) and two boosting circuits (that is,m=2) are disposed. As shown in FIG. 58, the oscillation circuit 210 isthe known oscillation circuit constituted by connecting in series aplurality of inverters and a plurality of NAND gates, and inputting theoutput of the final stage to the initial stage. The control signal EN isinputted to the NAND gate of the second stage of the oscillation circuit210 so that the operation of the oscillation circuit can be controlled.The NAND gate of the fifth stage of the oscillation circuit 210 and thecontrol signal vtx inputted to the output portion are used when the WLreset level generating circuit is compulsively stopped irrespective ofthe EN signal, such as during the test.

The first negative voltage generating circuit comprises the levelconverting circuit 220, the capacitor drive circuit 230-01, thecapacitor 240-01, the output circuit and the operation control circuit260-01. As shown in the drawing, the power source of the oscillationcircuit 210 is V2 and the power source of the capacitor drive circuit230-01 is V7 which is higher than V2. Therefore, the oscillation signalof the oscillation circuit 210 is first converted by the levelconverting circuit 220 to the level corresponding to V3 and is thenapplied to the capacitor drive circuit 230-01. When the output of thecapacitor drive circuit 230-01 is “H”, the gate of the P-channeltransistor of the capacitor 240-01 is grounded and reaches the groundlevel. In other words, the potential of the gate of the P-channeltransistor of the capacitor 240-01 becomes lower than the potential ofthe source and the drain. Next, when the output of the capacitor drivecircuit 230-01 changes to “L”, the gate of the P-channel transistor ofthe capacitor 240-01 is cut off from the ground, and the source and thedrain of the P-channel transistor of the capacitor 240-01 reach theground level. Since the gate potential of the P-channel transistor islower than the potential of the source and the drain as described above,the gate potential becomes the negative potential. This negativepotential is generated as V4. The operation control circuit 260-01 isthe switch for controlling the operation of the first negative voltagegenerating circuit. The first negative voltage generating circuitoperates when the control signal V4EN is “H” and stops its operationwhen V4EN is “L”.

The second negative voltage generating circuit comprises the capacitordrive circuit 230-02, the capacitor 240-02, the output circuit and theoperation control circuit 260-02. The power source V6 of the capacitordrive circuit 230-0 has a potential that is equal to, or lower than, V2.Therefore, the level converting circuit is not necessary. Theoscillation signal supplied from the oscillation circuit 210 to thesecond negative voltage generating circuit has a phase that is deviatedfrom the phase of the oscillation signal supplied to the first negativevoltage generating circuit. The negative potential is generated as V4′and controlled by the control signal V4′EN. The rest of theconstructions are the same as that of the first negative voltagegenerating circuit.

The first boosting circuit comprises the capacitor drive circuit 230-10,the capacitors 240-101 and 240-102, the output circuit and the operationcontrol circuit 260-11. The inverters 230-101 and 230-102 of thecapacitor drive circuit 230-10 are the drive unit of the capacitor. Thesignal P is supplied from the oscillation circuit 210 to the NAND gateof the operation control circuit 260-11. The control signal V5EN issupplied to the NAND gate so that the supply of the signal P in thecapacitor drive circuit, that is, the operation of the first boostingcircuit, can be controlled. The detailed explanation will be herebyomitted. The second boosting circuit has the same construction, too.

As described above, in the power source circuit according to the tenthembodiment, the four power source circuits, that is, the first andsecond negative voltage generating circuits and the first and secondboosting circuits, are driven by the oscillation signal supplied fromone oscillation circuit. Therefore, since only one oscillation circuit210 needs be disposed, the chip area as well as power consumption can bereduced.

FIG. 60 is a circuit diagram showing another structural example of theboosting circuit, and this circuit corresponds to the first boostingcircuit shown in FIG. 59. As shown in the diagram, this circuit isdifferent from the first boosting circuit of FIG. 59 in the gateconstruction of the capacitor drive circuit and the control of theoutput circuit. However, the basic operation is the same, and theexplanation in further detail will be omitted.

FIG. 61 is a circuit diagram showing the construction of the powersource generating circuit according to the eleventh embodiment of thepresent invention. In the tenth embodiment shown in FIG. 56, theeleventh embodiment constitutes one negative potential generatingcircuit and one boosting circuit by a plurality of units, respectively,and connecting their outputs in common. Therefore, other negativepotential generating circuits and boosting circuits may be disposedbesides the circuit shown in the drawing, and they may comprise aplurality of units as shown in the drawing. There are further disposedoutput level detecting circuits 270-1 and 270-2 for detecting the levelof the output of each unit connected in common. The oscillation signalshaving mutually different phases are supplied from the oscillationcircuit 210 to each negative potential generating circuit unit and eachboosting circuit unit. The eleventh embodiment is effective when thepumping capacity is large with respect to the cycle of the oscillationsignal. When the cycle of the oscillation circuit becomes short, acapacitor having a relatively large capacitance cannot be chargedsufficiently and current supply efficiency deteriorates. Therefore, thecycle of the oscillation signal cannot be much reduced. On the otherhand, it is preferred to shorten the cycle of the oscillation signal inorder to suppress an increase of the areas of the negative potentialgenerating circuit and the boosting circuit, and to restrict the currentconsumption. When the output of each unit is connected in common and theoscillation signal having a different phase is inputted to each unit asin the power source generating circuit of the eleventh embodiment,overall current efficiency does not deteriorate even when the cycle ofthe oscillation signal is so short as only a relatively small capacitorhas to be charged, since the current is supplied with other unitalternately.

The level detecting circuits 270-1 and 270-2 detect the level of thenegative potential and the level of the boosted potential, that areconnected in common (i.e., they detect whether the potentials are withinor outside a predetermined range), and control the operation of a part,or the whole, of the capacitor drive circuits 230-0 a to 230-0 k and230-1 a to 230-1I on the basis of the detection result. Thisconstruction is directed to operate a large number of units so as tosecure a sufficient amount of the current supply when the currentconsumption of all the negative potential generating circuits or of allthe boosting circuits is large, and to reduce power consumption bystopping the operation of a part of the units when current consumptionof the potential is small.

In the tenth and eleventh embodiments, the oscillation signal fordriving the capacitor is generated by the oscillation circuit in thechip. On the other hand, a synchronous DRAM (SDRAM), DDR-DRAM(Double-Data-Rate DRAM), etc., to which a clock is supplied from outsideand which makes it possible to execute a high-speed operation byconducting the input/output operations of the signal synchronously withthis clock, is available as a kind of DRAM. Since this clock is alwayssupplied when the chip is operative condition, signals similar to theoscillation signal can be generated by frequency-dividing the clocksignal from external. Next, the twelfth embodiment of the presentinvention, which is applied to such a semiconductor device, will beexplained.

FIG. 62 is a block circuit diagram showing the construction of thesemiconductor device according to the twelfth embodiment. As shown inthe circuit diagram, the semiconductor device 173 of the twelfthembodiment includes a clock input circuit 270 for receiving the clockCLK supplied from outside, a frequency dividing circuit 370 forfrequency-dividing the clock outputted from the clock input circuit 270and a plurality of power source circuits 171-0 to 171-n for generatingpower source voltages whose potentials are different from the externalpower supply voltage by driving the capacitor with the frequency dividedclock outputted from the frequency dividing circuit 370. The frequencydivided clocks supplied from the frequency dividing circuit 370 to eachpower source circuit 171-0 to 171-n may be the same frequency dividedclocks or the frequency divided clocks having the same cycle butdifferent phases or different frequencies of the frequency dividedclocks. Each power source generally circuit 171-0 to 171-n has thecapacitor drive circuit, the capacitor and the output circuit that areexplained in the eleventh embodiment, and the level converting circuitshown in FIG. 58 is used when a capacitor drive circuit having a highpower source voltage is used. Since the frequency dividing circuits areso arranged as to be in common with one another in the twelfthembodiment the chip area as well as power consumption can be reduced.

FIGS. 63A and 63B show structural examples of the circuits used for thefrequency dividing circuit 370 of the twelfth embodiment. In the case ofthe synchronously operating DRAMs, the clock signal supplied fromoutside has mostly an extremely high speed, and cannot as such be usedfor the capacitor drive circuit. Therefore, the frequency divided clockCK is generated by using the frequency dividing circuits shown in FIGS.63A and 63B. In FIG. 63A, a single stage ½ frequency dividing circuit isconstituted by combining a flip-flop circuit using two inverters and atransfer gate controlled by the clock CLK. A ½^(n) frequency dividingcircuit can be accomplished by connecting them in series of n stages ofthe ½ frequency dividing circuit. The detail explanation of FIG. 63Bwill be omitted, but this circuit is constituted by connecting n stagesof the ½ frequency dividing circuits in series in the same way as inFIG. 63A.

Though the embodiments of the present invention have thus beendescribed, the constructions of the tenth to twelfth embodiments can becombined in various ways as already described, and it is of importanceto employ the optimum method in accordance with the intendedapplication.

As explained above, in the semiconductor device having a plurality ofpower source circuits for generating different power source voltages bydriving the capacitor by the oscillation signal, the tenth to twelfthembodiments can reduce both the chip area and power consumption.

1. A semiconductor device including a word line drive circuit having thefunction of resetting a word line by driving said word line connected toa specific memory cell when said specific memory cell in a memory cellarray including a plurality of memory cells is returned from anactivated state to a standby state; wherein a reset level of said wordline drive circuit which is set when the reset operation of said wordline is executed can be switched between a first potential and a secondpotential.
 2. A semiconductor device according to claim 1, wherein areset level switch circuit unit for switching said first potential andsaid second potential of said reset level is disposed in said word linedrive circuit.
 3. A semiconductor device according to claim 1, whereinsaid reset level switch circuit for switching said first potential andsaid second potential of said reset level is disposed separately fromsaid word line drive circuit.
 4. A semiconductor device including aplurality of word line drive circuits each having the function ofresetting a word line by driving said word line connected to a specificmemory cell when said specific memory cell inside a memory cell arrayincluding a plurality of memory cells is returned from an activatedstate to a standby state; wherein a reset level switch circuit forswitching the reset level of a plurality of said word line drivecircuits which are set when the reset operation of said word line isexecuted, between a first potential and a second potential, is disposedseparately from said word line drive circuits, and the switchingoperation of said reset level between said first potential and saidsecond potential by said reset level switch circuit is collectivelyexecuted for a plurality of said word line drive circuits.
 5. Asemiconductor device according to claim 1, wherein said second potentialis set to a level lower than said first potential.
 6. A semiconductordevice according to claim 1, wherein said first potential of said resetlevel is a ground potential and said second potential is a potential ofa negative voltage level.
 7. A semiconductor device according to claim1, wherein the switching operation of said reset level to said firstpotential is executed before the reset operation of said word line isstarted.
 8. A semiconductor device according to claim 1, wherein theswitching operation of said reset level to said second potential isexecuted after said reset operation is started and the level of saidword line drops.
 9. A semiconductor device according to claim 1, whichfurther includes: a reset level switching control timing circuit forsetting in advance a period in which the level of said word line dropsto a predetermined level after the start of said reset operation, andfor switching said reset level from said first potential to said secondpotential after said period passes from the timing of the start of saidreset operation.
 10. A semiconductor device according to claim 1, whichfurther includes: a word line potential judging circuit for supervisingthe potential of said word line and switching said reset level from saidfirst potential to said second potential when it detects the drop of thepotential of said word line to a predetermined level.
 11. Asemiconductor device according to claim 1, wherein the switchingoperation of said reset level between said first potential and saidsecond potential is executed by using an activation signal and anon-activation signal for activating and non-activating a senseamplifier provided to said memory cell array.
 12. A semiconductor deviceaccording to claim 2, wherein said second potential is set to a levellower than said first potential.
 13. A semiconductor device according toclaim 2, wherein said first potential of said reset level is a groundpotential and said second potential is a potential of a negative voltagelevel.
 14. A semiconductor device according to claim 2, wherein theswitching operation of said reset level to said first potential isexecuted before the reset operation of said word line is started.
 15. Asemiconductor device according to claim 2, wherein the switchingoperation of said reset level to said second potential is executed aftersaid reset operation is started and the level of said word line drops.16. A semiconductor device according to claim 2, which further includes:a reset level switching control timing circuit for setting in advance aperiod in which the level of said word line drops to a predeterminedlevel after the start of said reset operation, and for switching saidreset level from said first potential to said second potential aftersaid period passes from the timing of the start of said reset operation.17. A semiconductor device according to claim 2, which further includes:a word line potential judging circuit for supervising the potential ofsaid word line and switching said reset level from said first potentialto said second potential when it detects the drop of the potential ofsaid word line to a predetermined level.
 18. A semiconductor deviceaccording to claim 2, wherein the switching operation of said resetlevel between said first potential and said second potential is executedby using an activation signal and a non-activation signal for activatingand non-activating a sense amplifier provided to said memory cell array.19. A semiconductor device according to claim 3, wherein said secondpotential is set to a level lower than said first potential.
 20. Asemiconductor device according to claim 3, wherein said first potentialof said reset level is a ground potential and said second potential is apotential of a negative voltage level.
 21. A semiconductor deviceaccording to claim 3, wherein the switching operation of said resetlevel to said first potential is executed before the reset operation ofsaid word line is started.
 22. A semiconductor device according to claim3, wherein the switching operation of said reset level to said secondpotential is executed after said reset operation is started and thelevel of said word line drops.
 23. A semiconductor device according toclaim 3, which further includes: a reset level switching control timingcircuit for setting in advance a period in which the level of said wordline drops to a predetermined level after the start of said resetoperation, and switching said reset level from said first potential tosaid second potential after said period passes from the timing of thestart of said reset operation.
 24. A semiconductor device according toclaim 3, which further includes: a word line potential judging circuitfor supervising the potential of said word line, and switching saidreset level from said first potential to said second potential when itdetects the drop of the potential of said word line to a predeterminedlevel.
 25. A semiconductor device according to claim 3, wherein theswitching operation of said reset level between said first potential andsaid second potential is executed by using an activation signal and anon-activation signal for activating and non-activating a senseamplifier provided to said memory cell array.
 26. A semiconductor deviceaccording to claim 4, wherein said second potential is set to a levellower than said first potential.
 27. A semiconductor device according toclaim 4, wherein said first potential of said reset level is a groundpotential and said second potential is a potential having a negativevoltage level.
 28. A semiconductor device according to claim 4, whereinthe switching operation of said reset level to said first potential isexecuted before the start of the reset operation of said word line. 29.A semiconductor device according to claim 4, wherein the switchingoperation of said reset level to said second potential is executed aftersaid reset operation is started and the level of said word line drops.30. A semiconductor device according to claim 4, which further includes:a reset level switching control timing circuit for setting in advance aperiod in which the level of said word line drops to a predeterminedlevel from the start of said reset operation, and switching said resetlevel from said first potential to said second potential after saidperiod passes from the timing of the start of said reset operation. 31.A semiconductor device according to claim 4, which further includes: aword line potential judging circuit for supervising the potential ofsaid word line and switching said reset level from said first potentialto said second potential when it detects the drop of the potential ofsaid word line to a predetermined level.
 32. A semiconductor deviceaccording to claim 4, wherein the switching operation of said resetlevel between said first potential and said second potential is executedby using an activation signal and a non-activation signal for activatingand non-activating a sense amplifier provided to said memory cell array.33. A semiconductor device according to claim 5, wherein the switchingoperation of said reset level to said first potential is executed beforethe start of the reset operation of said word line.
 34. A semiconductordevice according to claim 5, wherein the switching operation of saidreset level to said second potential is executed after said resetoperation is started and the level of said word line drops.
 35. Asemiconductor device according to claim 5, which further includes: areset level switching control timing circuit for setting in advance aperiod in which the level of said word line drops to a predeterminedlevel after the start of said reset operation, and switching said resetlevel from said first potential to said second potential after saidperiod passes from the timing of the start of said reset operation. 36.A semiconductor device according to claim 5, which further includes: aword line potential judging circuit for supervising the potential ofsaid word line, and switching said reset level from said first potentialto said second potential when it detects the drop of the potential ofsaid word line to a predetermined level.
 37. A semiconductor deviceaccording to claim 5, wherein the switching operation of said resetlevel between said first potential and said second potential is executedby using an activation signal and a non-activation signal for activatingand non-activating a sense amplifier provided to said memory cell array.38. A semiconductor device according to claim 6, wherein the switchingoperation of said reset level to said first potential is executed beforethe start of the reset operation of said word line.
 39. A semiconductordevice according to claim 6, wherein the switching operation of saidreset level to said second potential is executed after said resetoperation is started and the level of said word line drops.
 40. Asemiconductor device according to claim 6, which further includes: areset level switching control timing circuit for setting in advance aperiod in which the level of said word line drops to a predeterminedlevel after the start of said reset operation, and switching said resetlevel from said first potential to said second potential after saidperiod passes from the timing of the start of said reset operation. 41.A semiconductor device according to claim 6, which further includes: aword line potential judging circuit for supervising the potential ofsaid word line, and switching said reset level from said first potentialto said second potential when it detects the drop of the potential ofsaid word line to a predetermined level.
 42. A semiconductor deviceaccording to claim 6, wherein the switching operation of said resetlevel between said first potential and said second potential is carriedout by using an activation signal and a non-activation signal foractivating and non-activating a sense amplifier provided to said memorycell array.
 43. A semiconductor device including: a plurality of wordlines disposed in parallel; a plurality of bit lines extending in adirection perpendicular to the extending direction of said word lines; amemory cell array having a plurality of memory cells disposed in anarray form in such a manner as to correspond to said word lines and tosaid bit lines, and connected to corresponding ones of said word linesand said bit lines; and a word line reset level generating circuit forgenerating a negative potential; wherein non-selected ones of said wordlines are set to a negative potential by applying the output of saidword line reset level generating circuit to non-selected ones of saidword lines; and wherein said word line reset level generating circuitchanges the amount of a current supply of said negative potential inaccordance with the operation of said memory cell array.
 44. Asemiconductor device according to claim 43, which further includes: aword line reset level detecting circuit for detecting the output stateof said word line reset level generating circuit; and a word line resetlevel control circuit for controlling the operation of said word linereset level generating circuit on the basis of the detection result ofsaid reset level detecting circuit.
 45. A semiconductor device accordingto claim 44, wherein, when the output of said word line reset levelgenerating circuit is lower than a first predetermined voltage, saidreset level control circuit stops the operation of said word line resetlevel generating circuit; when the output of said word line reset levelgenerating circuit is higher than a second predetermined voltage, saidreset level control circuit operates said word line reset levelgenerating circuit so that the amount of the current supply thereofbecomes maximum; and when the output of said word line reset levelgenerating circuit is between said first and second predeterminedvoltages, said reset level control circuit controls the amount of thecurrent supply of said word line reset level generating circuit inaccordance with the operation of said memory cell array.
 46. Asemiconductor device according to claim 43, said semiconductor devicecomprising a plurality of banks; wherein said word line reset levelgenerating circuit comprises a plurality of circuit units correspondingto a plurality of said banks, and capable of operating independently;and wherein a plurality of said circuit units are selected and operatedin accordance with the operation of said memory cell array.
 47. Asemiconductor device according to claim 43, wherein said word line resetlevel generating circuit includes an oscillation circuit, a capacitorand a capacitor drive circuit for driving said capacitor, and a higherpotential of a power source of said capacitor drive circuit is higherthan a higher potential of a power source of said oscillation circuit.48. A semiconductor device according to claim 43, wherein said word linereset level generating circuit includes an oscillation circuit, acapacitor and a capacitor drive circuit for driving said capacitor, anda higher potential of a power source of said capacitor drive circuit isequal to a higher potential of a power source of said oscillationcircuit.
 49. A semiconductor device according to claim 43, wherein saidword line reset level generating circuit includes an oscillationcircuit, a capacitor and a capacitor drive circuit for driving saidcapacitor, and a higher potential of a power source of said capacitordrive circuit is lower than a higher potential of a power source of saidoscillation circuit.
 50. A semiconductor device according to claim 43,wherein said word line reset level generating circuit includes anoscillation circuit, a capacitor, a capacitor drive circuit for drivingsaid capacitor, and a power source switch circuit for switching theconnection of a power source line of higher potential of said capacitordrive circuit among a plurality of power source lines having differentpotentials.
 51. A semiconductor device according to claim 44, saidsemiconductor device comprising a plurality of banks; wherein said wordline reset level generating circuit comprises a plurality of circuitunits corresponding to a plurality of said banks, and capable ofoperating independently; and wherein a plurality of said circuit unitsare selected and operated in accordance with the operation of saidmemory cell array.
 52. A semiconductor device according to claim 44,wherein said word line reset level generating circuit includes anoscillation circuit, a capacitor and a capacitor drive circuit fordriving said capacitor, and a higher potential of a power source of saidcapacitor drive circuit is higher than a higher potential of a powersource of said oscillation circuit.
 53. A semiconductor device accordingto claim 44, wherein said word line reset level generating circuitincludes an oscillation circuit, a capacitor and a capacitor drivecircuit for driving said capacitor, and a higher potential of a powersource of said capacitor drive circuit is equal to a higher potential ofa power source of said oscillation circuit.
 54. A semiconductor deviceaccording to claim 44, wherein said word line reset level generatingcircuit includes an oscillation circuit, a capacitor and a capacitordrive circuit for driving said capacitor, and a higher potential of apower source of said capacitor drive circuit is lower than a higherpotential of a power source of said oscillation circuit.
 55. Asemiconductor device according to claim 44, wherein said word line resetlevel generating circuit includes an oscillation circuit, a capacitor, acapacitor drive circuit for driving said capacitor and a power sourceswitch circuit for switching the connection of a power source line ofhigher potential of said capacitor drive circuit among a plurality ofpower source lines having different potentials.
 56. A semiconductordevice according to claim 45, said semiconductor device comprising aplurality of banks; wherein said word line reset level generatingcircuit comprises a plurality of circuit units corresponding to aplurality of said banks and capable of operating independently; andwherein a plurality of said circuit units are selected and operated inaccordance with the operation of said memory cell array.
 57. Asemiconductor device according to claim 45, wherein said word line resetlevel generating circuit includes an oscillation circuit, a capacitorand a capacitor drive circuit for driving said capacitor, and a higherpotential of a power source of said capacitor drive circuit is higherthan a higher potential of a power source of said oscillation circuit.58. A semiconductor device according to claim 45, wherein said word linereset level generating circuit includes an oscillation circuit, acapacitor and a capacitor drive circuit for driving said capacitor, anda higher potential of a power source of said capacitor drive circuit isequal to a higher potential of a power source of said oscillationcircuit.
 59. A semiconductor device according to claim 45, wherein saidword line reset level generating circuit includes an oscillationcircuit, a capacitor and a capacitor drive circuit for driving saidcapacitor, and a higher potential of a power source of said capacitordrive circuit is lower than a higher potential of a power source of saidoscillation circuit.
 60. A semiconductor device according to claim 45,wherein said word line reset level generating circuit includes anoscillation circuit, a capacitor, a capacitor drive circuit for drivingsaid capacitor and a power source switch circuit for switching theconnection of a power source line of higher potential of said capacitordrive circuit among a plurality of power source lines having differentpotentials.
 61. A semiconductor device according to claim 50, whereinsaid power source switch circuit executes the switching operationbetween a power source line having a potential higher than a higherpotential of a power source of said oscillation circuit and a powersource line having a potential equal to a higher potential of a powersource of said oscillation circuit.
 62. A semiconductor device accordingto claim 55, wherein said power source switch circuit executes theswitching operation between a power source line having a potentialhigher than a higher potential of a power source of said oscillationcircuit and a power source line having a potential equal to a higherpotential of a power source of said oscillation circuit.
 63. Asemiconductor device according to claim 60, wherein said power sourceswitch circuit executes the switching operation between a power sourceline having a potential higher than a higher potential of a power sourceof said oscillation circuit and a power source line having a potentialequal to a higher potential of a power source of said oscillationcircuit.
 64. A semiconductor device according to claim 50, wherein saidpower source switch circuit executes the switching operation between apower source line having a potential equal to a higher potential of apower source of said oscillation circuit and a power source line havinga potential lower than a higher potential of a power source of saidoscillation circuit.
 65. A semiconductor device according to claim 55,wherein said power source switch circuit executes the switchingoperation between a power source line having a potential equal to ahigher potential of a power source of said oscillation circuit and apower source line having a potential lower than a higher potential of apower source of said oscillation circuit.
 66. A semiconductor deviceaccording to claim 60, wherein said power source switch circuit executesthe switching operation between a power source line having a potentialequal to a higher potential of a power source of said oscillationcircuit and a power source line having a potential lower than a higherpotential of a power source of said oscillation circuit.
 67. Asemiconductor device according to claim 43, wherein said word line resetlevel generating circuit includes an oscillation circuit, a capacitorand a capacitor drive circuit for driving said capacitor, and saidcapacitor drive circuit applies a single oscillation signal outputtedfrom said oscillation circuit to said capacitor.
 68. A semiconductordevice according to claim 43, wherein said word line reset levelgenerating circuit includes an oscillation circuit, a capacitor and acapacitor drive circuit for driving said capacitor, and said capacitordrive circuit applies a plurality of oscillation signals outputted fromsaid oscillation circuit to said capacitor.
 69. A semiconductor deviceaccording to claim 43, wherein said word line reset level generatingcircuit includes a plurality of oscillation circuit for outputtingoscillation signals having different frequencies, a capacitor, acapacitor drive circuit for driving said capacitor and a selectioncircuit for selecting the oscillation signal from a plurality of saidoscillation circuits to be supplied to said capacitor drive circuit. 70.A semiconductor device according to claim 43, wherein said word linereset level generating circuit includes a plurality of oscillationcircuits for outputting oscillation signals having differentfrequencies, a capacitor, a power source switch circuit for switchingthe connection of a power source line of higher potential of a capacitordrive circuit for driving said capacitor among a plurality of powersource lines having different potentials, and a selection circuit forselecting the oscillation signal from a plurality of said oscillationcircuits to be supplied to said capacitor drive circuit.
 71. Asemiconductor device according to claim 43, wherein said word line resetlevel generating circuit includes an oscillation circuit, a plurality ofcapacitor units, a plurality of capacitor drive circuit units each beingfor driving each of said capacitor units, and a switch for switching theinput of the oscillation signal outputted from said oscillation circuitto each of said capacitor drive circuit units, and said switch isswitched in accordance with the operation of said memory cell array. 72.A semiconductor device according to claim 44, wherein said word linereset level generating circuit includes an oscillation circuit, acapacitor and a capacitor drive circuit for driving said capacitor, andsaid capacitor drive circuit applies a single oscillation signaloutputted from said oscillation circuit to said capacitor.
 73. Asemiconductor device according to claim 44, wherein said word line resetlevel generating circuit includes an oscillation circuit, a capacitorand a capacitor drive circuit for driving said capacitor, and saidcapacitor drive circuit applies a plurality of oscillation signalsoutputted from said oscillation circuit to said capacitor.
 74. Asemiconductor device according to claim 44, wherein said word line resetlevel generating circuit includes a plurality of oscillation circuitsfor outputting oscillation signals having different frequencies, acapacitor, a capacitor drive circuit and a selection circuit forselecting the oscillation signal from a plurality of oscillationcircuits to be supplied to said capacitor drive circuit.
 75. Asemiconductor device according to claim 44, wherein said word line resetlevel generating circuit includes a plurality of oscillation circuitsfor outputting oscillation signals having different frequencies, acapacitor, a power source switch circuit for switching the connection ofa power source line of higher potential of a capacitor drive circuit fordriving said capacitor among a plurality of power source lines havingdifferent potentials, and a selection circuit for selecting theoscillation signal to be supplied to said capacitor drive circuit fromthe outputs of a plurality of said oscillation circuits.
 76. Asemiconductor device according to claim 44, wherein said word line resetlevel generating circuit includes an oscillation circuit, a plurality ofcapacitor units, a plurality of capacitor drive circuit units each beingfor driving each of said capacitor units, and a switch for switching theinput of the oscillation signal outputted from said oscillation circuitto each of said capacitor drive circuit units, and said switch isswitched in accordance with the operation of said memory cell array. 77.A semiconductor device according to claim 45, wherein said word linereset level generating circuit includes an oscillation circuit, acapacitor and a capacitor drive circuit for driving said capacitor, andsaid capacitor drive circuit applies a single oscillation signaloutputted from said oscillation circuit to said capacitor.
 78. Asemiconductor device according to claim 45, wherein said word line resetlevel generating circuit includes an oscillation circuit, a capacitorand a capacitor drive circuit for driving said capacitor, and saidcapacitor drive circuit applies a plurality of oscillation signalsoutputted from said oscillation circuit to said capacitor.
 79. Asemiconductor device according to claim 45, wherein said word line resetlevel generating circuit includes a plurality of oscillation circuitsfor outputting oscillation signals having different frequencies, acapacitor, a capacitor drive circuit for driving said capacitor and aselection circuit for selecting the oscillation signal from a pluralityof said oscillation circuits to be supplied to said capacitor drivecircuit.
 80. A semiconductor device according to claim 45, wherein saidword line reset level generating circuit includes a plurality ofoscillation circuits for outputting oscillation signals having differentfrequencies, a capacitor, a power source switch circuit for switchingthe connection of a power source line of higher potential of a capacitordrive circuit for driving said capacitor among a plurality of powersource lines having different potentials, and a selection circuit forselecting the oscillation signal from a plurality of said oscillationcircuits to be supplied to said capacitor drive circuit.
 81. Asemiconductor device according to claim 45, wherein said word line resetlevel generating circuit includes an oscillation circuit, a plurality ofcapacitor units, a plurality of capacitor drive circuit units each beingfor driving each of said capacitor units and a switch for switching theinput of the oscillation signal outputted from said oscillation circuitto each of said capacitor drive circuit units, and said switch isswitched in accordance with the operation of said memory cell array. 82.A semiconductor device according to claim 47, which further includes: aninternal regulator circuit for down-converting a power source voltagesupplied from outside, and a higher potential of a power source of saidoscillation circuit is supplied from said internal regulator circuit.83. A semiconductor device according to claim 52, which furtherincludes: an internal regulator circuit for down-converting a powersource voltage supplied from outside, and a higher potential of a powersource of said oscillation circuit is supplied from said internalregulator circuit.
 84. A semiconductor device according to claim 57,which further includes: an internal regulator circuit fordown-converting a power source voltage supplied from outside, and ahigher potential of a power source of said oscillation circuit issupplied from said internal regulator circuit.
 85. A semiconductordevice comprising a plurality of power source circuits each having anoscillation circuit and a capacitor, for generating a differentpotential by driving said capacitor by the oscillation signal outputtedfrom said oscillation circuit: wherein at least a part of a plurality ofsaid power source circuits shares in common said oscillation circuit,and drives different one of said capacitors by the oscillation signaloutputted from said common oscillation circuit.
 86. A semiconductordevice according to claim 85, wherein said power source circuit isequipped with an operation control circuit at an input portion to saidcapacitor drive circuit of the oscillation signal outputted from saidcommon oscillation circuit.
 87. A semiconductor device according toclaim 85, wherein said power source circuits sharing in common saidoscillation circuit generate different potentials.
 88. A semiconductordevice according to claim 85, wherein said common oscillation circuitoutputs a plurality of oscillation signals having different phases, andsaid capacitor is driven by one of a plurality of said oscillationsignals having different phases.
 89. A semiconductor device according toclaim 88, wherein said power source circuits having said capacitordriven by a plurality of said oscillation signals having differentphases generate the same potential, and the outputs of said power sourcecircuits are connected in common.
 90. A semiconductor device accordingto claim 89, wherein said power circuit includes: an operation controlcircuit provided at an input portion of said oscillation signaloutputted from said common oscillation circuit to said capacitor drivecircuit, and switching the operating state of said power source circuitbetween an operating state and a non-operating state; and a potentialdetecting circuit for detecting the potential generated by said powersource circuit; wherein said operation control circuit is controlled onthe basis of the detection result of said potential detecting circuit.91. A semiconductor device comprising a plurality of power sourcecircuits, each including a clock input circuit for receiving a clockinputted from outside and a capacitor, and generating differentpotentials by driving said capacitor by an internal clock for powersource outputted from said clock input circuit.
 92. A semiconductordevice according to claim 91, wherein said clock input circuit includesa frequency dividing circuit for frequency-dividing said clock, and theoutput of said frequency dividing circuit is outputted as the internalclock for power source.
 93. A semiconductor device according to claim85, wherein said semiconductor device is a dynamic random access memory.94. A semiconductor device according to claim 86, wherein saidsemiconductor device is a dynamic random access memory.
 95. Asemiconductor device according to claim 87, wherein said semiconductordevice is a dynamic random access memory.
 96. A semiconductor deviceaccording to claim 88, wherein said semiconductor device is a dynamicrandom access memory.
 97. A semiconductor device according to claim 91,wherein said semiconductor device is a dynamic random access memory. 98.A semiconductor device according to claim 92, wherein said semiconductordevice is a dynamic random access memory.